URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramBit.v] - Diff between revs 3 and 8

Rev 3	Rev 8
Line 18...	Line 18...
`begin`	`begin`

`if (reset)`	`if (reset)`
`begin`	`begin`
`bitRamOut = 1'b0;`	`bitRamOut = 1'b0;`
`$write (" module bitRam is reset ");`	`$write ("\nmodule bitRam is reset ");`
`end`	`end`

`else`	`else`
`begin`	`begin`

`if (bitRamEn)`	`if (bitRamEn)`
`begin`	`begin`
`if (bitRamRw) // read operation`	`if (bitRamRw) // read operation`
`begin`	`begin`
`bitRamOut = bitRam[bitRamAddr];`	`bitRamOut = bitRam[bitRamAddr];`
`$write (" reading bit-RAM : module bitRAM ");`	`// $write ("\nreading bit-RAM : module bitRAM ");`
`end`	`end`

`else // write operation`	`else // write operation`
`begin`	`begin`
`bitRam[bitRamAddr] = bitRamIn;`	`bitRam[bitRamAddr] = bitRamIn;`
`$write (" writing to bit-RAM : module bitRam ");`	`// $write ("\nwriting to bit-RAM : module bitRam ");`
`end`	`end`
`end`	`end`

`else`	`else`
`begin`	`begin`