URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramByte.v] - Diff between revs 3 and 8

Rev 3	Rev 8
Line 18...	Line 18...
`begin`	`begin`

`if (reset)`	`if (reset)`
`begin`	`begin`
byteRamOut = `byteRamLen'b0;	byteRamOut = `byteRamLen'b0;
`$write (" module byteRam is reset ");`	`$write ("\nmodule byteRam is reset ");`
`end`	`end`

`else`	`else`
`begin`	`begin`

Line 30...	Line 30...
`begin`	`begin`

`if (byteRamRw) // read operation`	`if (byteRamRw) // read operation`
`begin`	`begin`
`byteRamOut = byteRam[byteRamAddr];`	`byteRamOut = byteRam[byteRamAddr];`
`$write (" reading byte RAM : module byteRam ");`	`// $write ("\nreading byte RAM : module byteRam ");`
`end`	`end`


`else // write operation`	`else // write operation`
`begin`	`begin`
`byteRam[byteRamAddr] = byteRamIn;`	`byteRam[byteRamAddr] = byteRamIn;`
`$write (" writing to byte RAM : module byteRam ");`	`// $write ("\nwriting to byte RAM : module byteRam ");`
`end`	`end`

`end`	`end`

`else // if Enable = 0`	`else // if Enable = 0`