URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [tcEnableAndType.v] - Diff between revs 10 and 12

Rev 10	Rev 12
Line 52...	Line 52...
output wire [(`tcNumbers*`tcTypeLen)-1:0] typeOut;	output wire [(`tcNumbers*`tcTypeLen)-1:0] typeOut;

reg enables [`tcNumbers-1:0];	reg enables [`tcNumbers-1:0];
reg [`tcTypeLen-1:0] types [`tcNumbers-1:0];	reg [`tcTypeLen-1:0] types [`tcNumbers-1:0];

`always @ *`	`always @ (posedge entypeEn)`
`begin`	`begin`
`if (entypeEn)`	`if (entypeEn)`
`begin`	`begin`
`enables[tcAddr] = enIn;`	`enables[tcAddr] = enIn;`
`types[tcAddr] = typeIn;`	`types[tcAddr] = typeIn;`