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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module tcLoad (tcLoadEn, tcAddr, dnIn, ttIn, cuIn, cdIn, tcLoadOut);
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module tcLoad (tcAddr, dnIn, ttIn, cuIn, cdIn, tcLoadOut);
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input tcLoadEn;
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input [`tcAddrLen-1:0] tcAddr;
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input [`tcAddrLen-1:0] tcAddr;
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input [`tcNumbers-1:0] dnIn, ttIn, cuIn, cdIn;
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input [`tcNumbers-1:0] dnIn, ttIn, cuIn, cdIn;
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output [7:0] tcLoadOut;
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output [7:0] tcLoadOut;
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reg [`tcNumbers-1:0] dnInReg, ttInReg, cuInReg, cdInReg;
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wire dnSel, ttSel, cuSel, cdSel;
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wire dnSel, ttSel, cuSel, cdSel;
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always @ *
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begin
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dnInReg = dnIn;
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ttInReg = ttIn;
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cuInReg = cuIn;
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cdInReg = cdIn;
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end
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assign dnSel = dnInReg[tcAddr];
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assign ttSel = ttInReg[tcAddr];
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assign cuSel = cuInReg[tcAddr];
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assign cdSel = cdInReg[tcAddr];
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assign tcLoadOut = {4'b0, dnSel, ttSel, cuSel, cdSel};
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assign dnSel = dnIn[tcAddr];
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assign ttSel = ttIn[tcAddr];
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assign cuSel = cuIn[tcAddr];
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assign cdSel = cdIn[tcAddr];
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assign tcLoadOut = {4'b0, cdSel, cuSel, ttSel, dnSel};
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endmodule
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endmodule
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