| Line 45... |
Line 45... |
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
, rx, tx
|
, rx, tx
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
|
, MISO, MOSI, SCK
|
|
`endif
|
|
|
|
);
|
);
|
|
|
|
|
input clk,reset;
|
input clk,reset;
|
input [`inputNumber-1:0] IN;
|
input [`inputNumber-1:0] IN;
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| Line 61... |
Line 57... |
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
input rx;
|
input rx;
|
output tx;
|
output tx;
|
`endif
|
`endif
|
|
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`ifdef SPI_peripheral
|
|
input MISO;
|
|
output MOSI, SCK;
|
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`endif
|
|
|
|
// wires (interconnects) of execution unit
|
// wires (interconnects) of execution unit
|
|
|
wire [`instAddrLen-1:0] pcOut;
|
wire [`instAddrLen-1:0] pcOut;
|
wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
|
wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
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| Line 90... |
Line 82... |
wire accEnOutc;
|
wire accEnOutc;
|
wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
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wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
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wire aluEnc;
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wire aluEnc;
|
wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
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wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
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wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
|
wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
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wire inputReadOutc, outputRwOutc;
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wire outputRwOutc;
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`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
|
wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc;
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`endif
|
`endif
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
wire uartReadOutc, uartWriteOutc;
|
wire uartReadOutc, uartWriteOutc;
|
wire [7:0] uartDataOut;
|
wire [7:0] uartDataOut;
|
wire rxEmpty, txFull;
|
wire rxEmpty, txFull;
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`endif
|
`endif
|
`ifdef SPI_peripheral
|
|
wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
|
|
`endif
|
|
|
|
wire branchOut;
|
wire branchOut;
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wire [`accMuxSelLen-1:0] accMuxSelOut;
|
wire [`accMuxSelLen-1:0] accMuxSelOut;
|
wire accEnOut;
|
wire accEnOut;
|
wire [`op2MuxSelLen-1:0] op2MuxSelOut;
|
wire [`op2MuxSelLen-1:0] op2MuxSelOut;
|
wire aluEn;
|
wire aluEn;
|
wire [`aluOpcodeLen-1:0] aluOpcodeOut;
|
wire [`aluOpcodeLen-1:0] aluOpcodeOut;
|
wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
|
wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
|
wire inputReadOut, outputRwOut;
|
wire outputRwOut;
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
|
wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
|
`endif
|
`endif
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
wire uartReadOut, uartWriteOut;
|
wire uartReadOut, uartWriteOut;
|
`endif
|
`endif
|
`ifdef SPI_peripheral
|
|
wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
|
|
`endif
|
|
|
|
|
|
|
|
// wires (interconnects) of timer & counter
|
// wires (interconnects) of timer & counter
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
| Line 138... |
Line 123... |
wire [(`tcNumbers*2)-1:0] typeWires;
|
wire [(`tcNumbers*2)-1:0] typeWires;
|
wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
|
wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
|
|
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
|
|
|
wire [7:0] spiStatOut, spiBufOut;
|
|
`endif
|
|
|
|
|
|
wire clk_d, clk_t;
|
wire clk_d, clk_t;
|
reg [10:0] cnt = 0;
|
reg [10:0] cnt = 0;
|
|
|
always @ (posedge clk or posedge reset)
|
always @ (posedge clk or posedge reset)
|
| Line 196... |
Line 176... |
ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
|
ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
|
|
|
|
|
//-------- Control Unit Module Instance
|
//-------- Control Unit Module Instance
|
|
|
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
|
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, instField2[8:7],
|
branchOutc,
|
|
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
|
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
|
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
|
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
|
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
|
`endif
|
`endif
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
, uartReadOutc, uartWriteOutcc
|
, uartReadOutc, uartWriteOutcc
|
`endif
|
`endif
|
`ifdef SPI_peripheral
|
|
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
|
|
`endif
|
|
|
|
);
|
);
|
|
|
|
|
|
|
// pipeline register
|
// pipeline register
|
|
|
|
|
|
|
ppReg2 PipeLine_Reg2 (clk,
|
ppReg2 PipeLine_Reg2 (clk,
|
branchOutc,
|
|
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
|
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
|
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
|
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
|
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
|
`endif
|
`endif
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
, uartReadOutc, uartWriteOutcc
|
, uartReadOutc, uartWriteOutcc
|
`endif
|
`endif
|
`ifdef SPI_peripheral
|
|
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
|
|
`endif
|
|
, instField1
|
, instField1
|
|
|
, branchOut,
|
,accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
|
accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
|
|
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
|
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
|
inputReadOut, outputRwOut
|
outputRwOut
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
|
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut
|
`endif
|
`endif
|
|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
, uartReadOut, uartWriteOut
|
, uartReadOut, uartWriteOut
|
`endif
|
`endif
|
|
|
`ifdef SPI_peripheral
|
|
, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
|
|
`endif
|
|
|
|
, instField2
|
, instField2
|
);
|
);
|
|
|
|
|
//-------- Execute Unit Modules Instances
|
//-------- Execute Unit Modules Instances
|
| Line 267... |
Line 234... |
, tcLoadOut, tcAccOut
|
, tcLoadOut, tcAccOut
|
`endif
|
`endif
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
, uartDataOut, {rxEmpty, txFull}
|
, uartDataOut, {rxEmpty, txFull}
|
`endif
|
`endif
|
`ifdef SPI_peripheral
|
|
, spiStatOut, spiBufOut
|
|
`endif
|
|
, accMuxOut
|
, accMuxOut
|
);
|
);
|
|
|
|
|
accumulator acc (accMuxOut, accEnOut, accOut);
|
accumulator acc (accMuxOut, accEnOut, accOut);
|
| Line 311... |
Line 275... |
// optional
|
// optional
|
|
|
`ifdef timerAndCounter_peripheral
|
`ifdef timerAndCounter_peripheral
|
|
|
|
|
|
|
|
|
tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);
|
tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);
|
|
|
tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
|
tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
|
|
|
tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
|
tcReset tcResetModule(tcResetEnOut, accOut[0], instField2[3:0], resetWires);
|
|
|
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
|
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
|
|
|
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
|
tcLoad tcLoadModule(instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
|
|
|
timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
|
timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
|
|
|
timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
|
timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
|
|
|
| Line 364... |
Line 326... |
|
|
uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
|
uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
|
|
|
`endif
|
`endif
|
|
|
//---------- SPI Modules
|
|
// optional
|
|
|
|
`ifdef SPI_peripheral
|
|
|
|
|
|
spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
|
|
|
|
|
|
`endif
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
