| Line 56... |
Line 56... |
`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
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wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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wire uartReadOutc, uartWriteOutc;
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wire uartReadOutc, uartWriteOutc;
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wire [7:0] uartDataOut;
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wire rxEmpty, txFull;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
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wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
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`endif
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`endif
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| Line 86... |
Line 88... |
// wires (interconnects) of timer & counter
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// wires (interconnects) of timer & counter
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
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wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
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wire [7:0] tcAccumOut;
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wire [7:0] tcAccOut;
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wire [7:0] tcLoadOut;
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wire [7:0] tcLoadOut;
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wire [`tcNumbers-1:0] enWires;
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wire [`tcNumbers-1:0] enWires;
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wire [`tcNumbers-1:0] resetWires;
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wire [`tcNumbers-1:0] resetWires;
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wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
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wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
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wire [(`tcNumbers*2)-1:0] typeWires;
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wire [(`tcNumbers*2)-1:0] typeWires;
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| Line 116... |
Line 118... |
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//-------- Fetch Unit Module Instances
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//-------- Fetch Unit Module Instances
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// all necessary
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// all necessary
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pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
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pgmCounter ProgramCounter (clk, reset, branchOutc, instField[9:0], pcOut);
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// instruction ROM is declared using xilinx primitive
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// instruction ROM is declared using xilinx primitive
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RAMB16_S18 rom ( .DI(),
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RAMB16_S18 rom ( .DI(),
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.DIP(),
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.DIP(),
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| Line 130... |
Line 132... |
.SSR(1'b0),
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.SSR(1'b0),
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.CLK(clk),
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.CLK(clk),
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.DO(romOut),
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.DO(romOut),
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.DOP());
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.DOP());
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instReg IntructionRegister (romOut, instOpCode, instField);
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// instReg IntructionRegister (romOut, instOpCode, instField);
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// pipeline register
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// pipeline register
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wire [`instOpCodeLen-1:0] instOpCode1;
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wire [`instOpCodeLen-1:0] instOpCode1;
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wire [`instFieldLen-1:0] instField1;
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wire [`instFieldLen-1:0] instField1;
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wire [`instFieldLen-1:0] instField2;
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wire [`instFieldLen-1:0] instField2;
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ppReg1 PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);
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ppReg1 PipeLine_Reg1 (clk, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
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//-------- Control Unit Module Instance
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//-------- Control Unit Module Instance
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controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
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controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
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| Line 213... |
Line 215... |
accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut
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accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, tcLoadOut, tcAccOut
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, tcLoadOut, tcAccOut
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartDataOut
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, uartDataOut, {rxEmpty, txFull}
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, spiStatOut, spiBufOut
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, spiStatOut, spiBufOut
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`endif
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`endif
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, accMuxOut
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, accMuxOut
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| Line 259... |
Line 261... |
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tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
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tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
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tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
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tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
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tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
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tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
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tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
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tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
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