| Line 28... |
Line 28... |
output MOSI, SCK;
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output MOSI, SCK;
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`endif
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`endif
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// wires (interconnects) of execution unit
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// wires (interconnects) of execution unit
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|
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wire [`instLen-1:0] pcOut;
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wire [`instAddrLen-1:0] pcOut;
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wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
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wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
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wire [`instOpCodeLen-1:0] instOpCode;
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wire [`instOpCodeLen-1:0] instOpCode;
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wire [`instFieldLen-1:0] instField;
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wire [`instFieldLen-1:0] instField;
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|
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wire [7:0] accMuxOut;
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wire [7:0] accMuxOut;
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| Line 98... |
Line 98... |
wire [(`tcNumbers*2)-1:0] typeWires;
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wire [(`tcNumbers*2)-1:0] typeWires;
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wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
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wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
|
|
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`endif
|
`endif
|
|
|
// wires (interconnects) of UART
|
`ifdef SPI_peripheral
|
|
|
`ifdef UART_peripheral
|
|
|
|
|
|
|
|
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wire [7:0] spiStatOut, spiBufOut;
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`endif
|
`endif
|
|
|
// wires (interconnects) of SPI
|
|
|
|
`ifdef SPI_peripheral
|
wire clk_d, clk_t;
|
|
reg [10:0] cnt = 0;
|
|
|
`endif
|
always @ (posedge clk or posedge reset)
|
|
begin
|
|
if (reset)
|
|
begin
|
|
cnt =0;
|
|
end
|
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else
|
|
begin
|
|
cnt = cnt + 1'b1;
|
|
end
|
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end
|
|
|
|
assign clk_d = cnt[0];
|
|
assign clk_t = cnt[10];
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|
|
|
|
|
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//-------- Fetch Unit Module Instances
|
//-------- Fetch Unit Module Instances
|
// all necessary
|
// all necessary
|
|
|
pgmCounter ProgramCounter (clk, reset, branchOutc, instField[9:0], pcOut);
|
pgmCounter ProgramCounter (clk_d, reset, branchOutc, instField[9:0], pcOut);
|
|
|
|
|
// instruction ROM is declared using xilinx primitive
|
// instruction ROM is declared using xilinx primitive
|
RAMB16_S18 rom ( .DI(),
|
RAMB16_S18 rom ( .DI(),
|
.DIP(),
|
.DIP(),
|
.ADDR(pcOut),
|
.ADDR(pcOut),
|
.EN(1'b1),
|
.EN(1'b1),
|
.WE(),
|
.WE(),
|
.SSR(1'b0),
|
.SSR(1'b0),
|
.CLK(clk),
|
.CLK(clk_d),
|
.DO(romOut),
|
.DO(romOut),
|
.DOP());
|
.DOP());
|
|
|
// instReg IntructionRegister (romOut, instOpCode, instField);
|
// rom CodeMem (pcOut, romOut);
|
|
|
|
|
// pipeline register
|
// pipeline register
|
|
|
wire [`instOpCodeLen-1:0] instOpCode1;
|
wire [`instOpCodeLen-1:0] instOpCode1;
|
wire [`instFieldLen-1:0] instField1;
|
wire [`instFieldLen-1:0] instField1;
|
wire [`instFieldLen-1:0] instField2;
|
wire [`instFieldLen-1:0] instField2;
|
|
|
ppReg1 PipeLine_Reg1 (clk, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
|
ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
|
|
|
|
|
//-------- Control Unit Module Instance
|
//-------- Control Unit Module Instance
|
|
|
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
|
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
|
| Line 269... |
Line 277... |
|
|
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
|
tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
|
|
|
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
|
tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
|
|
|
timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
|
timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
|
|
|
timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
|
timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
|
|
|
timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
|
timer timer2 (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
|
|
|
timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
|
timer timer3 (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
|
|
|
counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
|
counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
|
|
|
counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
|
counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
|
|
|
