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Line 8... |
\makebox[\textwidth]{\framebox[9cm]{\rule{0pt}{9cm}
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\makebox[\textwidth]{\framebox[9cm]{\rule{0pt}{9cm}
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\includegraphics[width=8cm]{img/cpu_symbol.png}}}
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\includegraphics[width=8cm]{img/cpu_symbol.png}}}
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\caption{CPU module interface\label{cpu_symbol}}
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\caption{CPU module interface\label{cpu_symbol}}
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\end{figure}
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\end{figure}
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the CPU module is not meant to be used directly. Instead, the MCU module
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the CPU module is not meant to be used directly. Instead, the SoC module
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described in section ~\ref{mcu_module} should be used.\\
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described in chapter ~\ref{soc_module} should be used.\\
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The following sections will describe the CPU structure and interfaces.\\
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The following sections will describe the CPU structure and interfaces.\\
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\section{Bus Architecture}
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\section{Bus Architecture}
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\label{bus_architecture}
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\label{bus_architecture}
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| Line 44... |
Line 44... |
bus(es).\\
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bus(es).\\
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Note that the basic cpu module (mips\_cpu) is meant to be connected to
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Note that the basic cpu module (mips\_cpu) is meant to be connected to
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internal, synchronous BRAMs only (i.e. the cache BRAMs). Some of its
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internal, synchronous BRAMs only (i.e. the cache BRAMs). Some of its
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outputs are not registered because they needn't be. The parent module
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outputs are not registered because they needn't be. The parent module
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(called 'mips\_mcu') has its outputs registered to limit $t_{co}$ to
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(called 'mips\_soc') has its outputs registered to limit $t_{co}$ to
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acceptable values.\\
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acceptable values.\\
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\subsection{Code and data read bus interface}
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\subsection{Code and data read bus interface}
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\label{code_data_buses}
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\label{code_data_buses}
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| Line 169... |
Line 169... |
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In short, the 'mem\_wait' input will unconditionally stall all pipeline
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In short, the 'mem\_wait' input will unconditionally stall all pipeline
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stages as long as it is active. It is meant to be used by the cache at cache
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stages as long as it is active. It is meant to be used by the cache at cache
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refills.\\
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refills.\\
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In short, the cache/memory controller stops the cpu for all data/code
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The cache/memory controller stops the cpu for all data/code
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misses for as long as it takes to do a line refill. The current cache
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misses for as long as it takes to do a line refill. The current cache
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implementation does refills in order (i.e. not 'target address first').
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implementation does refills in reverse order (i.e. not 'target address first').
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Note that external memory wait states are a separate issue. They too are
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Note that external memory wait states are a separate issue. They too are
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handled in the cache/memory controller. See section~\ref{cache} on the memory
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handled in the cache/memory controller. See section~\ref{cache} on the memory
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controller.
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controller.
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| Line 269... |
Line 269... |
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All read and write ports of the register bank are synchronous. The read
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All read and write ports of the register bank are synchronous. The read
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ports belong logically to stage 1 and the write port to stage 2.\\
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ports belong logically to stage 1 and the write port to stage 2.\\
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IMPORTANT: though the register bank read port is synchronous, its data can
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IMPORTANT: though the register bank read port is synchronous, its data can
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be used in stage 1 because it is read early (the read port is loaded at the
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be used in stage 1 because it is read early (the read address port is loaded at the
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same time as the instruction opcode). That is, a small part of the
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same time as the instruction opcode). That is, a small part of the
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instruction decoding is done on stage FETCH-1. Bearing in mind that the code
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instruction decoding is done on stage FETCH-1, by feeding the source
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register index field straight from the code bus to the register bank BRAM.
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Bearing in mind that the code cache
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ram is meant to be the exact same type of block as the register bank (or
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ram is meant to be the exact same type of block as the register bank (or
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faster if the register bank is implemented with distributed RAM), and we
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faster if the register bank is implemented with distributed RAM), and we
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will cram the whole ALU delay plus the reg bank delay in stage 1, it does
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will cram the whole ALU delay plus the reg bank delay in stage 1, it does
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not hurt moving a tiny part of the decoding to the previous cycle.\\
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not hurt moving a tiny part of the decoding to the previous cycle.\\
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| Line 452... |
Line 455... |
The following instruction is aborted even if it is a load or a jump, and
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The following instruction is aborted even if it is a load or a jump, and
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traps work as specified even from a delay slot -- in that case, the address
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traps work as specified even from a delay slot -- in that case, the address
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saved to EPF is not the victim instruction's but the preceding jump
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saved to EPF is not the victim instruction's but the preceding jump
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instruction's as explained in \cite[p.~64]{see_mips_run}.\\
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instruction's as explained in \cite[p.~64]{see_mips_run}.\\
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Plasma used to save in epc the address of the instruction after break or
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Plasma CPU used to save in epc the address of the instruction after break or
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syscall, and used an unstandard vector address (0x03c). This core will go
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syscall, and used an unstandard vector address (0x03c). This core will go
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the standard R3000 way instead.\\
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the standard R3000 way instead.\\
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Note that the epc register is not used by any instruction other than mfc0.
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Note that the epc register is not used by any instruction other than mfc0.
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RTE is implemented and works as per R3000 specs.\\
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RTE is implemented and works as per R3000 specs.\\
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