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'Hello world' demo and a memory tester. Only the 'hello' demo is included
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'Hello world' demo and a memory tester. Only the 'hello' demo is included
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in pre-generated form, the others have to be built using the included
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in pre-generated form, the others have to be built using the included
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makefiles -- assuming you have a mips toolchain.\\
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makefiles -- assuming you have a mips toolchain.\\
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'Pre-generated' in this context means that all the vhdl files necessary for
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'Pre-generated' in this context means that all the vhdl files necessary for
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building the demo are already included with the project, and the only
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building the demo are already included with the project, including the
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configuration package that contains the program's object code, and the only
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tool needed is the synthesis tool.
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tool needed is the synthesis tool.
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The pregenerated demo is included just for convenience, so that you can
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The pregenerated demo is included just for convenience, so that you can
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launch some small application on hardware without installing a C toolchain.\\
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launch some small application on hardware without installing a C toolchain.\\
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This choice tells the synth tool what speed grade and chip package
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This choice tells the synth tool what speed grade and chip package
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we'll be targetting.
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we'll be targetting.
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\item 'Next' your way out of the new project wizard.
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\item 'Next' your way out of the new project wizard.
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\item Add to the project all the vhdl files in /vhdl and /vhdl/demo,
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\item Add to the project all the vhdl files in /vhdl and /vhdl/demo,
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except mips\_cache\_stub.vhdl and sdram\_controller.vhdl.
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except mips\_cache\_stub.vhdl and sdram\_controller.vhdl.
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\item Add to the project all the vhdl files in /vhdl/SoC.
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\item Select file c2sb\_demo.vhdl as top.
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\item Select file c2sb\_demo.vhdl as top.
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\item Import pin constraints file (assignments-\textgreater import assignments).
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\item Import pin constraints file (assignments-\textgreater import assignments).
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\item Create a clock constraint for signal clk (51 MHz or some other
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\item Create a clock constraint for signal clk (51 MHz or some other
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suitable speed which gives us some minimal slack).
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suitable speed which gives us some minimal slack).
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\item In the device settings window, click "Device and pin options...".
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\item In the device settings window, click "Device and pin options...".
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\item Select tab "Dual-Purpose pins".
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\item Select tab "Dual-Purpose pins".
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\item Double-click on nCEO value column and select "use as regular I/O".
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\item Double-click on nCEO value column and select "use as regular I/O".
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IMPORTANT: otherwise the synthesis will fail; we need to use a FPGA
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IMPORTANT: otherwise the synthesis will fail; we need to use a FPGA
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pin that happens to be dual-purpose (programming and regular).
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pin that happens to be dual-purpose (programming and regular).
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\item Select 'balanced' optimization.
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\item Select 'speed' optimization.
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\item Save the project and synthesize.
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\item Save the project and synthesize.
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\item Make sure the clock constraint is met (timing analyzer report).
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\item Make sure the clock constraint is met (timing analyzer report).
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There is a random element to the synthesis process, as you know,
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There is a random element to the synthesis process, as you know,
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but the core as shipped should pass the constraint.
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but the core as shipped should pass the constraint.
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\item Program the FPGA from Quartus-2
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\item Program the FPGA from Quartus-2
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\item If you have a terminal hooked to the serial port (19200/8/N/1) you
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\item If you have a terminal hooked to the serial port (19200/8/N/1) you
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should see a welcome message after depressing the reset button.
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should see a welcome message after depressing the reset button.
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(by default this is pusbutton 2).
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(by default this is pushbutton 2).
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\end{enumerate}
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\end{enumerate}
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In the present version, the synthesis will produce a lot of warnings. The
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In the present version, the synthesis will produce a lot of warnings. The
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ugliest are about unused pins and an undeclared clock line. None of them
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ugliest are about unused pins and an undeclared clock line. None of them
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should be really scary.\\
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should be really scary.\\
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Line 87... |
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The 'hello' demo should be easily portable to any board which has all of
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The 'hello' demo should be easily portable to any board which has all of
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this:
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this:
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\begin{itemize}
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\begin{itemize}
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\item An FPGA capable enough (the demo uses internal memory for code)
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\item An FPGA capable enough (the demo uses internal memory for code).
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\item At least 4KB of 16-bit wide external, asynchronous, old-fashioned SRAM
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\item At least 4KB of 16-bit wide external, asynchronous, old-fashioned SRAM.
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\item A reset pin (possibly a pushbutton)
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\item A reset pin (possibly a pushbutton).
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\item A clock input (uart modules assume 50MHz, see below)
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\item A clock input (uart modules assume 50MHz, see below).
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\item RXD and TXD UART pins, plus a connector, header or whatever
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\item RXD and TXD UART pins, plus a connector, header or whatever.
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\end{itemize}
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\end{itemize}
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The only modules that care at all about clock rate are the UART
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The only module that care at all about clock rate is the UART embedded into
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modules. They are hardwired to 19200 bauds when clocked at 50MHz, so if you
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the SoC module. It's hardwired to 19200 bauds when clocked at 50MHz, so if you
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use a different frequency you must edit the generics in the demo entity
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use a different frequency you must edit the generics in the demo entity
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accordingly.\\
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accordingly -- the demo generics are passed all the way down to whatever
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Be aware that these uart modules have been used a lot in other projects but
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module needs them.\\
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have not been tested with a wide range of clock rates; they should work but
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The UART has hardly been tested at clock rates other than 50MHz and has not
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you have been warned.\\
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passed any independent test bench; try the core first at 50 MHz.\\
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Though there is no reset control logic, the reset input is synchronized
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Though there is no reset control logic, the reset input is synchronized
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internally, so you can use a raw pushbutton -- you may trigger multiple
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internally, so you can use a raw pushbutton -- you may trigger multiple
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resets if your pushbutton isn't tight but you'll never cause metastability
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resets if your pushbutton isn't tight but you'll never cause metastability
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trouble.\\
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trouble.\\
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Assuming you take care of all of the above, the easiest way I see to port
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Assuming you take care of all of the above, the easiest way I see to port
|
the demo is just editing the top module ports ('/vhdl/demo/c2sb\_demo.vhdl')
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the demo is just editing the top module ports ('/vhdl/demo/c2sb\_demo.vhdl')
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to match your board setup.\\
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to match your board setup. The only tricky part is the interface to FLASH
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and SDRAM.\\
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All the code in this project is vendor agnostic (or should be, I have only
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All the code in this project is vendor agnostic (or should be, I have only
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tried it on Quartus and ISE). Specifically, it does not instantiate memory
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tried it on Quartus and ISE). Specifically, it does not instantiate memory
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blocks (relying instead on memory inference) or clock managers or buffers.
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blocks (relying instead on memory inference) or clock managers or buffers.
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This has its drawbacks but is an stated goal of the project -- in the long
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This has its drawbacks but is an stated goal of the project -- in the long
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On the other hand, when you get to the \emph{maze of twisty little passages}
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On the other hand, when you get to the \emph{maze of twisty little passages}
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you know you have a computer, finished or not. The 'Adventure' demo is
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you know you have a computer, finished or not. The 'Adventure' demo is
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great as a confidence builder.\\
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great as a confidence builder.\\
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Besides, running Adventure on a computer built by myself is something
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Besides, running Adventure on a computer built by myself is something
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I just wanted to do :)\\
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I've always wanted to do :)\\
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No newline at end of file
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No newline at end of file
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