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\clearpage
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\clearpage
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This file contains usage instructions and notes about the Ion CPU core project.
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This file contains usage instructions and notes about the Ion CPU core project.
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The core structure is briefly explained in sections 1 to 4. The rest of this
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The core structure is briefly explained in sections 1 to 5. The rest of this
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doc describes other aspects of the project: code samples, utility scripts,
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doc describes other aspects of the project: code samples, utility scripts,
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etc.\\
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etc.\\
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This document is not yet a full reference on the Ion core. Instead, it should be
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This document is not yet a full reference on the Ion core or a data sheet.
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taken as a companion and commentary to the source code.\\
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Instead, it should be taken as a companion and commentary to the source code.\\
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This document assumes you know in some depth the MIPS-I architecture. Terms and
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This document assumes you know in some depth the MIPS-I architecture. Terms and
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concepts from \cite['See MIPS Run']{see_mips_run} and
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concepts from \cite['See MIPS Run']{see_mips_run} and
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\cite['IDT R3K Reference Manual']{r3k_ref_man} are used throughout the text.\\
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\cite['IDT R3K Reference Manual']{r3k_ref_man} are used throughout the text.\\
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\item 4KB direct-mapped, writethrough data cache.
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\item 4KB direct-mapped, writethrough data cache.
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\item Simplified CP0, mostly compatible to R3000.
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\item Simplified CP0, mostly compatible to R3000.
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\item All unimplemented opcodes trigger the proper traps.
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\item All unimplemented opcodes trigger the proper traps.
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\item Includes minimalistic memory handler with interfaces for external
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\item Includes minimalistic memory handler with interfaces for external
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SRAM (or FLASH) on 8- and 16-bit data bus.
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SRAM (or FLASH) on 8- and 16-bit data bus.
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\item Size and speed compares favorably to other free MIPS cores.
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\item Size and speed comparable to other free MIPS cores.
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\item Fully sinchronous (rising clock edge only). No latches.
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\item Fully sinchronous (rising clock edge only). No latches.
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\item Source HDL is vendor independent (Though it has only been tested on
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\item Source HDL is fully vendor independent (Only tested on
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Xilinx and Altera synthesis tools).
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Xilinx and Altera synthesis tools).
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\end{enumerate}
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\end{enumerate}
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\end{framed}
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\end{framed}
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\subsection{Missing features to be implemented eventually}
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\subsection{Missing features to be implemented eventually}
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\begin{enumerate}
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\begin{enumerate}
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\item Hardware interrupts not implemented.
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\item Hardware interrupts not implemented.
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\item Memory handler does not support dynamic RAM.
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\item Memory handler does not support dynamic RAM.
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\item Caches are not configurable or parametrizable.
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\item Caches are not configurable or parametrizable.
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\item Documentation is disastrously inadequate.
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\item Real documentation (specs doc \& data sheet) missing.
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\end{enumerate}
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\end{enumerate}
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\end{framed}
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\end{framed}
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