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In short, the simulation test bench is meant to run any of the code samples
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In short, the simulation test bench is meant to run any of the code samples
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provided in directory /src, under a controlled environment, while logging
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provided in directory /src, under a controlled environment, while logging
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the cpu state to a text log file.\\
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the cpu state to a text log file.\\
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This log file can then be compared to a log file generated by a software
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This log file can then be compared to a log file generated by a software
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simulator for the same code sample (see section 5.1). The software
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simulator for the same code sample (see section \ref{sw_simulator}). The software
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simulator is the 'golden model' against which the cpu is tested, so any
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simulator is the 'golden model' against which the cpu is tested, so any
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difference between both log files means trouble.\\
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difference between both log files means trouble.\\
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This method is far easier than building a fully automated test bench, and
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This method is far easier than building a fully automated test bench, and
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much more convenient and reliable than a visual inspection of the simulation
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much more convenient and reliable than a visual inspection of the simulation
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state.\\
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state.\\
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In addition to the main log file, there is a console log file to which all
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In addition to the main log file, there is a console log file to which all
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data written to the UART is logged (see section~\ref{uart_logging}).\\
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data written to the UART is logged (see section~\ref{uart_logging}).\\
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There are a few simulation test bench templates in the /src directory, which
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are used by all the code samples.\\
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The only ones actually used are '/src/code\_rom\_template.vhdl' and
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'/src/sim\_params\_template.vhdl'. The others
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are remnants of previous versions that will be removed ASAP.\\
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The template in file '/src/code\_rom\_template.vhdl' is filled with object
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code meant to be run from internal FPGA BRAM. This is how we load bootstrap
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code into our FPGA. The resulting file is '/vhdl/demo/code\_rom\_pkg.vhdl'
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and is used by both the simulation test bench and the synthesizable MCU.\\
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The template in file '/src/sim\_params\_template.vhdl' is filled with
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simulation parameters (such as the simulation length, etc.) and the resulting
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file is written as '/vhdl/tb/sim\_params\_pkg.vhdl'. This file is only used
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by the simulation test bench.
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All of this template filling is done by a python script (/src/bin2hdl.py)
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The simulation test bench can be found in file '/vhdl/tb/mips\_tb.vhdl'.
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which is invoked from the makefiles and explained in section xxx.\\
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This test bench is meant to be used with all the code samples.
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Each of the code samples configures the simulation test bench with certain
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parameters (such as simulation length or memory sizes) and of course each
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sample has a different object code to be run. The way to pass these
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parameters to the simulation is through a simulation package, in file
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'/vhdl/tb/sim\_params\_pkg.vhdl'.
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This file is generated from a template whenever you 'make' each code sample
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(see section~\ref{samples}). The package is built using oe of the
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provided tools, 'build\_pkg', explained in section ~\ref{build_pkg}.
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Note that all code samples share the same vhdl files: you need to run the
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Note that all code samples share the same vhdl files: you need to run the
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makefile target 'sim' for the sample you want to simulate; that will
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makefile target 'sim' for the sample you want to simulate; that will
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overwrite the two files mentioned above. So there's no vhdl file that is
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overwrite the package file mentioned above. So there's no vhdl file that is
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specific to a particular code sample.\\
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specific to a particular code sample.\\
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The actual test bench entity is at '/vhdl/tb/mips\_tb.vhdl' and is shared
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by all the code samples.\\
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While the test benches and sample code are good enough to catch MOST errors
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While the test benches and sample code are good enough to catch MOST errors
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in the full system (i.e. cache included) they don't help with diagnostic;
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in the full system (i.e. cache included) they don't help with diagnostic;
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once you know there's an error, and the approximate address where it's
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once you know there's an error, and the approximate address where it's
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triggered (approximate because of the cache) you have to dig into the
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triggered (approximate because of the cache) you have to dig into the
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simulation waveforms to find it. It's easier than it seems.\\
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simulation waveforms to find it.\\
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\section{Running the Simulation}
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\section{Running the Simulation}
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\label{running_the_simulation}
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\label{running_the_simulation}
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A simulation script can be found at '/sim/mips\_tb.do'. This script will
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A simulation script can be found at '/sim/mips\_tb.do'. This script will
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All the code samples are run with the same script.\\
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All the code samples are run with the same script.\\
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The test bench files mentioned in the previous section are automatically
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The test bench files mentioned in the previous section are automatically
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generated for each of the sample programs. This is automatically done by the
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generated for each of the sample programs. This is automatically done by the
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sample code makefile,
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sample code makefile,
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assuming you have a MIPS cross-toolchain in your computer (see section~\ref{code_samples}).\\
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assuming you have a MIPS cross-toolchain in your computer (see section~\ref{samples}).\\
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For convenience, a pre-generated mips\_tb.vhdl is included so you can launch
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For convenience, a pre-generated file 'sim\_params\_pkg.vhdl' is included
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a simulation without having to install toolchains, etc. The code is that
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so you can launch a simulation without having to install toolchains, etc.
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of the 'hello world' sample.\\
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The code is that of the 'hello world' sample.\\
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I guess that if you are interested in this sort of stuff then you probably
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I guess that if you are interested in this sort of stuff then you probably
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know more about Modelsim than I do. Yet, here's a step-by-step guide to
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know more about Modelsim than I do. Yet, here's a step-by-step guide to
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simulating the 'hello world' sample:
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simulating the 'hello world' sample:
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\begin{enumerate}
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\begin{enumerate}
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\item Run 'make hello\_sim' from directory '/src/hello'.
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\item Run 'make hello\_sim' from directory '/src/hello'.
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This will compile the program sources, build the necessary binary object
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This will compile the program sources, build the necessary binary object
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files and then create the two package files mentioned above.\\
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files and then create the package file mentioned above.\\
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Read the makefile and comments in the python script '/src/bin2hdl.py'
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Read the makefile and comments in the python script '/src/bin2hdl.py'
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for details.\\
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for details.\\
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ALTERNATIVELY, if you don't have a toolchain you can just skip this
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ALTERNATIVELY, if you don't have a toolchain you can just skip this
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step and use the default vhdl files provided, which are those of the
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step and use the default vhdl files provided, which are those of the
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This means that for example a long chain of NOPs, or MOVEs that don't change
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This means that for example a long chain of NOPs, or MOVEs that don't change
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register values, will not be seen in the log file. This is on purpose.\\
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register values, will not be seen in the log file. This is on purpose.\\
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Events are logged with the address of the instruction that triggered
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Events are logged with the address of the instruction that triggered
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the change. This holds true even for load instructions.\\
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the change. This holds true even for load instructions.\\
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Early versions of the project logged the address of the
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preceding instruction -- it was confusing and I have fixed it.\\
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The simulation log file is stored by default in modelsim's working directory
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The simulation log file is stored by default in modelsim's working directory
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(see above). I don't provide any automated script to do the comparison, you
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(see above). I don't provide any automated script to do the comparison, you
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should use whatever diff tool you like best.\\
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should use whatever diff tool you like best.\\
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