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Line 18... |
Target 'sim' will build the simulation test bench package files as described
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Target 'sim' will build the simulation test bench package files as described
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in section~\ref{logic_simulation}.
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in section~\ref{logic_simulation}.
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Target 'demo' will build a synthesizable demo; it will compile the sample
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Target 'demo' will build a synthesizable demo; it will compile the sample
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sources and place the resulting object code in file
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sources and place the resulting object code in file
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'/vhdl/demo/code\_rom\_pkg.vhdl' (note that the 'sim' target has to do this
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'/vhdl/SoC/bootstrap\_code\_pkg.vhdl'.\\
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too).\\
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The build process will produce two or more binary files ('*.code' and
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The build process will produce two or more binary files ('*.code' and
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'*.data', or '*.bin') that can be run on the software simulator, plus a
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'*.data', or '*.bin') that can be run on the software simulator, plus a
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listing file (*.lst) handy for debugging.\\
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listing file (*.lst) handy for debugging.\\
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All projects include a DOS batch file 'swsim.bat' that invokes the
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All projects include a DOS batch file 'swsim.bat' that invokes the
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software simulator with the proper parameters. As an example, these are the
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software simulator with the proper parameters. As an example, these are the
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contents of the 'swsim.bat' file for the 'hello' demo:
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contents of the 'swsim.bat' file for the 'hello' demo:
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\needspace{8\baselineskip}
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\begin{verbatim}
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\begin{verbatim}
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@rem Run software simulator in hands-off mode
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@rem Run software simulator in hands-off mode
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..\..\tools\slite\slite\bin\Debug\slite.exe ^
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..\..\tools\slite\slite\bin\Debug\slite.exe ^
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--bram=hello.code ^
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--bram=hello.code ^
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--trigger=bfc00000 ^
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--trigger=bfc00000 ^
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| Line 49... |
Line 49... |
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The python script 'bin2hdl.py' is used to insert binary data on vhdl
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The python script 'bin2hdl.py' is used to insert binary data on vhdl
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templates.
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templates.
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Assuming you have Python 2.5 or later in your machine, call the script with:
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Assuming you have Python 2.5 or later in your machine, call the script with:
|
|
|
|
\needspace{1\baselineskip}
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\begin{verbatim}
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\begin{verbatim}
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python bin2hdl.py --help
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python bin2hdl.py --help
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\end{verbatim}\\
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\end{verbatim}\\
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to get a short description (see section~\ref{python_script}).
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to get a short description (see section~\ref{python_script}).
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\section{Support Code}
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\label{support_code}
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\subsection{Bootstrap Code}
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\label{asm_bootstrap_code}
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File \emph{'/src/common/bootstrap.s'} contains the reset code and the stub
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interrupt handler.
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This code is meant to be placed at the reset vector address; in the present
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revision of the project, the bootstrap code would be placed in the
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bootstrap BRAM of the SoC module (see section ~\ref{bootstrap_code}). It
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can be placed in external memory if the SoC memory map and the makefiles are
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altered accordingly.
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The reset code initializes both I-Cache and D-Cache and jumps to symbol
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\texttt{'entry'} with the CPU in kernel mode and interrupts disabled.
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The interrupt code is somewhat more elaborate but nevertheless is still
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a stub. The interrupt code will find out the cause of the interrupt and will
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proceed.
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Table ~\ref{tab_irq_handling} shows interrupt sources recognized in the
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current version, and how the interrupt code deals with them.
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\begin{table}[h]
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\caption{Interrupt handling\label{tab_irq_handling}}
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\begin{tabularx}{\textwidth}{ l|X }
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\toprule
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Cause & Processing \\
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\midrule
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SYSCALL instruction & Return immediately (STUB). \\
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BREAK instruction & Return immediately (STUB). \\
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Invalid opcode & Return immediately (STUB). \\
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Unimplemented MIPS-32 opcode & Emulate opcode. \\
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\bottomrule
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\end{tabularx}
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\end{table}
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Please note that the interrupt code does not even \emph{know} there is
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such a thing as a hardware interrupt -- hardware interrupts are not
|
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implemented yet in the CPU.
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As can be seen, most of the interrupt processing is missing, replaced by
|
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stubs. Eventually, those stubs will be replaced with calls to C functions
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that will be defined in the supporting libraries. I have yet to work out
|
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exactly how to do it without reinventing the wheel.
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|
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The only interrupt processing that is performed (even if only partially) is
|
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the emulation of \emph{some} MIPS-32 opcodes.
|
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\subsection{MIPS-32 Opcode Emulation}
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\label{mips32_opcode_emulation}
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I have found out that most MIPS toolchains target the MIPS-32 architecture
|
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and can only be made to work with the MIPS-I architecture with some
|
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difficulty. This applies specially to the C support libraries, where
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MIPS-32 opcodes are used occasionally.
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Other reasons, such as the availability of MIPS-32 ports of
|
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uClinux, make at least partial compatibility to MIPS-32 very desirable.
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On the other hand, extending the core to implement the full MIPS-32 specs (as
|
|
opposed to the far simpler MIPS-I) might not be possible without running
|
|
into a patent minefield -- I may be wrong in this.
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|
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Therefore, I have chosen to just emulate whatever subset of the
|
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MIPS-32 ISA is enough to overcome the above obstacles. I have run some
|
|
experiments with uClinux and have found out that only a few MIPS-32 opcodes
|
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need to be emulated -- see table ~\ref{tab_emulated_opcodes}.
|
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|
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\begin{table}[h]
|
|
\caption{Emulated MIPS-32 opcodes\label{tab_emulated_opcodes}}
|
|
\begin{tabularx}{\textwidth}{ l|X }
|
|
\toprule
|
|
Opcode & Emulation \\
|
|
\midrule
|
|
EXT & Fully emulated. \\
|
|
INS & Fully emulated. \\
|
|
CLO & Fully emulated. \\
|
|
CLZ & Fully emulated. \\
|
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\midrule
|
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MUL (3-reg version) & To Be Done. \\
|
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LWL & To Be Done. \\
|
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LWR & To Be Done. \\
|
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SWL & To Be Done. \\
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SWR & To Be Done. \\
|
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\bottomrule
|
|
\end{tabularx}
|
|
\end{table}
|
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Opcode emulation is implemented in file \emph{/src/common/opcode\_emu.s}.
|
|
|
|
The emulation code has been tested (code sample \emph{'opcodes'}) but is
|
|
still unfinished: not only are there opcodes to be emulated, as can
|
|
be seen in table ~\ref{tab_emulated_opcodes}, but the emulation does NOT
|
|
work when the MIPS-32 opcode is in a delay slot; or more precisely, the
|
|
jump instruction of the delay slot is not emulated as it should -- this is
|
|
just work to be done, nothing specially difficult.
|
|
|
|
|
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If the trapped MIPS-32 opcode is not one of the emulated opcodes, it is
|
|
ignored exactly as if it was a NOP. A flag is raised in a special, reserved
|
|
area of the BSS segment -- see the source for details. Eventually the trap
|
|
handling will be complete and unimplemented MIPS-32 opcodes will be dealt
|
|
with as undefined opcodes.
|
|
|
|
Note that opcode emulation can be disabled in the makefiles, by defining
|
|
symbol \texttt{NO\_EMU\_MIPS32} when assembling \emph{bootstrap.s}.
|
|
|
|
|
|
\subsection{C Startup Code}
|
|
\label{c_startup_code}
|
|
|
|
File \emph{'/src/common/c\_startup.s'} contains the C startup code used
|
|
in all C code samples.
|
|
|
|
This startup code does what's usual in these cases, namely:
|
|
|
|
\begin{enumerate}
|
|
\item Initialize the stack at the end of the bss area.
|
|
\item Clear the bss area.
|
|
\item Move the data section from FLASH to RAM (if applicable).
|
|
\item Call main().
|
|
\item Freeze in endless loop after main() returns, if it does.
|
|
\end{enumerate}
|
|
|
|
|
|
See the makefile of any of the C code samples for examples on how to
|
|
assemble, configure and link the startup code.
|
|
|
|
|
|
\subsection{C Support Library Replacement}
|
|
\label{libsoc}
|
|
|
|
The core will eventually be tested with one of the regular, free libc
|
|
replacement libraries available. It isn't yet because building those
|
|
libraries for a MIPS-I target (i.e. with no MIPS-32 stuff mixed in) has
|
|
turned out to be much more difficult than I had anticipated.
|
|
|
|
In order to be able to use the C toolchain and provide some code samples in
|
|
C, I have built a minimalistic libc replacement called 'libsoc'. The
|
|
source code can be found in \emph{/src/common/libsoc/src}.
|
|
|
|
This mini-libc provides only those C support functions I have found
|
|
necessary so far; it will be extended with new functionality as I add more
|
|
code samples, until I can finally use some real C library.
|
|
|
|
Apart from a number of utility functions that the C runtime needs, libsoc
|
|
provides the following:
|
|
|
|
\begin{itemize}
|
|
\item Floating point support (SW, float and double).
|
|
\item \texttt{putchar} and \texttt{getchar} using the SoC UART.
|
|
\item Replacement for the built-in \texttt{printf} provided by gcc.
|
|
\end{itemize}
|
|
|
|
That's it. Yet, even this little is enough to run the Adventure demo...
|
|
|
|
All the source code has been lifted from the original Plasma supporting code
|
|
or has been scavenged from the net -- see credits in the file headers.
|
|
|
|
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No newline at end of file
|
No newline at end of file
|
