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\chapter{Tools}
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\chapter{Tools}
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\label{tools}
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\label{tools}
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Directory '/tools' of the project includes a few tools -- small C or Python
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programs purpose-built for this project.
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What follows is a brief description of each of the tools. This document
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won't go into the implementation or usage details. The tools themselves have
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brief usage instructions and for any further details the user must read
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the source code.
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\section{MIPS Software Simulator}
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\section{MIPS Software Simulator}
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\label{sw_simulator}
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\label{sw_simulator}
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Plasma project includes a MIPS-I simulator made by Steve Rhoads, called
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Plasma project includes a MIPS-I simulator made by Steve Rhoads, called
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'mlite.c'. According the the author, it was used as a golden model for the
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'mlite.c'. According the the author, it was used as a golden model for the
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vhdl test bench.
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vhdl test bench.
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\item Does not simulate the cache at all.
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\item Does not simulate the cache at all.
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\end{itemize}
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\end{itemize}
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Each code sample includes a DOS batch file named 'swsim.bat' that runs the
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Each code sample includes a DOS batch file named 'swsim.bat' that runs the
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simulator in batch mode.\\
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simulator in batch mode. Note that the BAT file invokes a windows binary
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which is included in the SVN repository and should be immediately useable
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after checkout.\\
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The program includes usage help (a short description of the command line
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The program includes usage help (a short description of the command line
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parameters). The source code (very simple and straighforward) is includef in
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parameters). The source code (very simple and straighforward) is included in
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the project. The BAT files provide an usage example. And anyone who is
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the project. The BAT files provide an usage example. And anyone who is
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interested and finds trouble can always contact me.
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interested and finds trouble can always contact me.
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For all these reasons I think it is not necessary to explain the simulator
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For all these reasons I think it is not necessary to explain the simulator
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in detail. Nothing to do with laziness, as you can see.\\
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in detail. Nothing to do with laziness, as you can see.\\
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simulated memory sizes and the code and data addresses.\\
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simulated memory sizes and the code and data addresses.\\
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The hardcoded log file name is "sw\_sim\_log.txt" and it is generated in the
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The hardcoded log file name is "sw\_sim\_log.txt" and it is generated in the
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same directory from which the simulator is run.\\
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same directory from which the simulator is run.\\
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\section{Configuration Package Builder Script build\_pkg.py}
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\label{python_script}
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This tools is used to build a simulation and synthesis configuration
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package.
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The generated package contains configuration constants used by the
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simulation test bench \emph{'mips\_tb.vhdl'} and by the hardware demo
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\emph{'c2sb\_demo.vhdl'}.
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It too includes memory initialization constants containing object code,
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used to initialize simulated and inferred memories, both in simulation
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and in synthesis.
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In the code samples, this script is used to generate two separate packages
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for simulation and synthesis. Please refer to the makefiles for detailed
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usage examples.
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\section{Conversion Script bin2hdl.py}
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\section{Conversion Script bin2hdl.py}
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\label{python_script}
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\label{python_script}
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\begin{figure*}[ht]
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\begin{center}
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{\small
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\framebox[7in]{
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\begin{minipage}[t]{6.0in}
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NOTE: This script was used in previous versions of the project -- it came
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in handy to initialize byte-sliced memories when the caches were under
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development.
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It has been abandoned because it was far too complicated and no longer
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necessary. The VHDL
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templates it refers to and the script itself have been moved from the /src
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directory to their own subdirectory in /tools.
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It is being retained in case it becomes useful again but it is no longer
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used.
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\end{minipage}
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}
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}
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\end{center}
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\label{lb}
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\end{figure*}
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This Python script reads one or more binary files and 'inserts' them in a
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This Python script reads one or more binary files and 'inserts' them in a
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vhdl template. It makes the
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vhdl template. It makes the
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conversion from binary to vhdl strings and slices the data in byte columns,
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conversion from binary to vhdl strings and slices the data in byte columns,
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as required by the RAM implementation (in which each byte in a word is
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as required by the RAM implementation (in which each byte in a word is
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stored in a different RAM with a separate WE, 4 blocks in all).\\
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stored in a different RAM with a separate WE, 4 blocks in all).\\
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