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[/] [ion/] [trunk/] [src/] [bin2hdl.py] - Diff between revs 124 and 190

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Line 4... Line 4...
examples.
examples.
"""
"""
import sys
import sys
import getopt
import getopt
import math
import math
 
import datetime
 
 
 
 
def usage():
def usage():
    print ""
    print ""
    print "usage:"
    print "usage:"
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    print "ALL of the following arguments should be given, in any order:"
    print "ALL of the following arguments should be given, in any order:"
    print "{c|code} <filename>        Code binary image file name"
    print "{c|code} <filename>        Code binary image file name"
    print "{v|vhdl} <filename>        VHDL template"
    print "{v|vhdl} <filename>        VHDL template"
    print "{a|architecture} <name>    Name of target VHDL architecture"
    print "{a|architecture} <name>    Name of target VHDL architecture"
    print "{e|entity} <name>          Name of target VHDL entity"
    print "{e|entity} <name>          Name of target VHDL entity"
 
    print "{n|name} <name>            Name of project (used only in comment)"
    print "{o|output} <filename>      Target VHDL file name"
    print "{o|output} <filename>      Target VHDL file name"
    print "code_size <number>         Size of bram memory in words (decimal)"
    print "code_size <number>         Size of bram memory in words (decimal)"
    print "data_size <number>         Size of data memory in words (decimal)"
    print "data_size <number>         Size of data memory in words (decimal)"
    print "flash_size <number>        Size of flash memory in words (decimal)"
    print "flash_size <number>        Size of flash memory in words (decimal)"
    print "(note the flash and xram info are used in simulation only)"
    print "(note the flash and xram info are used in simulation only)"
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    print "Tags like @data31@ and @data20@ etc. can be used to initialize"
    print "Tags like @data31@ and @data20@ etc. can be used to initialize"
    print "memories in 16-bit buses, also split in byte columns.\n"
    print "memories in 16-bit buses, also split in byte columns.\n"
    print "Other template tags are replaced as follows:"
    print "Other template tags are replaced as follows:"
    print "@entity_name@         : Name of entity in target vhdl file"
    print "@entity_name@         : Name of entity in target vhdl file"
    print "@arch_name@           : Name of architecture in target vhdl file"
    print "@arch_name@           : Name of architecture in target vhdl file"
 
    print "@fileinfo@            : Info about the generated vhdl file"
    print "@sim_len@             : Length of simulation in clock cycles"
    print "@sim_len@             : Length of simulation in clock cycles"
    print "@code_table_size@     : Size of code RAM block, in words"
    print "@code_table_size@     : Size of code RAM block, in words"
    print "@code_addr_size@      : ceil(Log2(@code_table_size@))"
    print "@code_addr_size@      : ceil(Log2(@code_table_size@))"
    print "@data_table_size@     : Size of data RAM block, in words"
    print "@data_table_size@     : Size of data RAM block, in words"
    print "@data_addr_size@      : ceil(Log2(@data_table_size@))"
    print "@data_addr_size@      : ceil(Log2(@data_table_size@))"
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    data_filename = ""          # file with xram contents ('data')
    data_filename = ""          # file with xram contents ('data')
    flash_filename = ""         # file with flash contents ('flash')
    flash_filename = ""         # file with flash contents ('flash')
    vhdl_filename = ""          # name of vhdl template file
    vhdl_filename = ""          # name of vhdl template file
    entity_name = "mips_tb"     # name of vhdl entity to be generated
    entity_name = "mips_tb"     # name of vhdl entity to be generated
    arch_name = "testbench"     # name of vhdl architecture to be generated
    arch_name = "testbench"     # name of vhdl architecture to be generated
 
    proj_name = "<?>"           # name of project as shown in file info comment
    target_filename = "tb.vhdl" # name of target vhdl file
    target_filename = "tb.vhdl" # name of target vhdl file
    indent = 4                  # indentation for table data, in spaces
    indent = 4                  # indentation for table data, in spaces
    code_table_size = -1        # size of VHDL table
    code_table_size = -1        # size of VHDL table
    data_table_size = -1        # size of VHDL table
    data_table_size = -1        # size of VHDL table
    flash_table_size = 32;      # default size of flash table in 32-bit words
    flash_table_size = 32;      # default size of flash table in 32-bit words
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    simulation_length = 22000   # length of logic simulation in clock cycles
    simulation_length = 22000   # length of logic simulation in clock cycles
 
 
    #
    #
 
 
    try:
    try:
        opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
        opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:n:",
        ["help", "code=", "data=", "vhdl=", "architecture=",
        ["help", "code=", "data=", "vhdl=", "architecture=",
 
         # long name args that have short version
         "entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
         "entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
 
         "name=",
 
         # long name args that DON'T have short version
         "code_size=", "data_size=", "flash_size="])
         "code_size=", "data_size=", "flash_size="])
    except getopt.GetoptError, err:
    except getopt.GetoptError, err:
        print ""
        print ""
        print err
        print err
        usage()
        usage()
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            flash_filename = arg
            flash_filename = arg
        elif opt in ("-a", "--architecture"):
        elif opt in ("-a", "--architecture"):
            arch_name = arg
            arch_name = arg
        elif opt in ("-e", "--entity"):
        elif opt in ("-e", "--entity"):
            entity_name = arg
            entity_name = arg
 
        elif opt in ("-n", "--name"):
 
            proj_name = arg
        elif opt in ("-i", "--indent"):
        elif opt in ("-i", "--indent"):
            indent = int(arg)
            indent = int(arg)
        elif opt in ("-t", "--log_trigger"):
        elif opt in ("-t", "--log_trigger"):
            log_trigger_addr = "X\"%08X\"" % (int(arg,16))
            log_trigger_addr = "X\"%08X\"" % (int(arg,16))
        elif opt in ("-s", "--sim_len"):
        elif opt in ("-s", "--sim_len"):
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       code_table_size < 0 or data_table_size<0:
       code_table_size < 0 or data_table_size<0:
        print "Some mandatory parameter is missing\n"
        print "Some mandatory parameter is missing\n"
        usage()
        usage()
        sys.exit(2)
        sys.exit(2)
 
 
 
    # Once all cmd line argumets are parsed, build secondary stuff out of them.
 
    # Contents of 1st vhdl comment line
 
    fileinfo = "File built automatically for project '" + proj_name + \
 
               "' by bin2hdl.py" # + \
 
               #str(datetime.datetime.now().strftime("%Y-%m-%d %H:%M"))
 
 
 
 
    #---------------------------------------------------------------------------    
    #---------------------------------------------------------------------------    
    # Read BRAM initialization file, if any
    # Read BRAM initialization file, if any
    try:
    try:
        fin = open(code_filename, "rb")
        fin = open(code_filename, "rb")
        code = fin.read()
        code = fin.read()
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                "@data0@","@data1@","@data2@","@data3@",
                "@data0@","@data1@","@data2@","@data3@",
                "@data31@", "@data20@",
                "@data31@", "@data20@",
                "@data-32bit@",
                "@data-32bit@",
                "@flash@",
                "@flash@",
                "@entity_name@","@arch_name@",
                "@entity_name@","@arch_name@",
 
                "@fileinfo@",
                "@sim_len@",
                "@sim_len@",
                "@xram_size@",
                "@xram_size@",
                "@code_table_size@","@code_addr_size@",
                "@code_table_size@","@code_addr_size@",
                "@data_table_size@","@data_addr_size@",
                "@data_table_size@","@data_addr_size@",
                "@prom_size@",
                "@prom_size@",
                "@log_trigger_addr@"];
                "@log_trigger_addr@"];
    replacement = vhdl_code_strings + vhdl_data_strings + \
    replacement = vhdl_code_strings + vhdl_data_strings + \
                 [vhdl_flash_string,
                 [vhdl_flash_string,
                  entity_name, arch_name,
                  entity_name, arch_name,
 
                  fileinfo,
                  str(simulation_length),
                  str(simulation_length),
                  str(data_table_size),
                  str(data_table_size),
                  str(code_table_size),
                  str(code_table_size),
                  str(int(math.floor(math.log(code_table_size,2)))),
                  str(int(math.floor(math.log(code_table_size,2)))),
                  str(data_table_size),
                  str(data_table_size),

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