| Line 4... |
Line 4... |
examples.
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examples.
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"""
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"""
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import sys
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import sys
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import getopt
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import getopt
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import math
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import math
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import datetime
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def usage():
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def usage():
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print ""
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print ""
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print "usage:"
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print "usage:"
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| Line 16... |
Line 17... |
print "ALL of the following arguments should be given, in any order:"
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print "ALL of the following arguments should be given, in any order:"
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print "{c|code} <filename> Code binary image file name"
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print "{c|code} <filename> Code binary image file name"
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print "{v|vhdl} <filename> VHDL template"
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print "{v|vhdl} <filename> VHDL template"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{n|name} <name> Name of project (used only in comment)"
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print "{o|output} <filename> Target VHDL file name"
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print "{o|output} <filename> Target VHDL file name"
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print "code_size <number> Size of bram memory in words (decimal)"
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print "code_size <number> Size of bram memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "flash_size <number> Size of flash memory in words (decimal)"
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print "flash_size <number> Size of flash memory in words (decimal)"
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print "(note the flash and xram info are used in simulation only)"
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print "(note the flash and xram info are used in simulation only)"
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| Line 41... |
Line 43... |
print "Tags like @data31@ and @data20@ etc. can be used to initialize"
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print "Tags like @data31@ and @data20@ etc. can be used to initialize"
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print "memories in 16-bit buses, also split in byte columns.\n"
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print "memories in 16-bit buses, also split in byte columns.\n"
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print "Other template tags are replaced as follows:"
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print "Other template tags are replaced as follows:"
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print "@entity_name@ : Name of entity in target vhdl file"
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print "@entity_name@ : Name of entity in target vhdl file"
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print "@arch_name@ : Name of architecture in target vhdl file"
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print "@arch_name@ : Name of architecture in target vhdl file"
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print "@fileinfo@ : Info about the generated vhdl file"
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print "@sim_len@ : Length of simulation in clock cycles"
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print "@sim_len@ : Length of simulation in clock cycles"
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print "@code_table_size@ : Size of code RAM block, in words"
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print "@code_table_size@ : Size of code RAM block, in words"
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print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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| Line 180... |
Line 183... |
data_filename = "" # file with xram contents ('data')
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data_filename = "" # file with xram contents ('data')
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flash_filename = "" # file with flash contents ('flash')
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flash_filename = "" # file with flash contents ('flash')
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vhdl_filename = "" # name of vhdl template file
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vhdl_filename = "" # name of vhdl template file
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entity_name = "mips_tb" # name of vhdl entity to be generated
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entity_name = "mips_tb" # name of vhdl entity to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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proj_name = "<?>" # name of project as shown in file info comment
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target_filename = "tb.vhdl" # name of target vhdl file
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target_filename = "tb.vhdl" # name of target vhdl file
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indent = 4 # indentation for table data, in spaces
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indent = 4 # indentation for table data, in spaces
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code_table_size = -1 # size of VHDL table
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code_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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flash_table_size = 32; # default size of flash table in 32-bit words
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flash_table_size = 32; # default size of flash table in 32-bit words
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| Line 193... |
Line 197... |
simulation_length = 22000 # length of logic simulation in clock cycles
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simulation_length = 22000 # length of logic simulation in clock cycles
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#
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#
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try:
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try:
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:n:",
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["help", "code=", "data=", "vhdl=", "architecture=",
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["help", "code=", "data=", "vhdl=", "architecture=",
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# long name args that have short version
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"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
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"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
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"name=",
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# long name args that DON'T have short version
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"code_size=", "data_size=", "flash_size="])
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"code_size=", "data_size=", "flash_size="])
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except getopt.GetoptError, err:
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except getopt.GetoptError, err:
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print ""
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print ""
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print err
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print err
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usage()
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usage()
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| Line 223... |
Line 230... |
flash_filename = arg
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flash_filename = arg
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elif opt in ("-a", "--architecture"):
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elif opt in ("-a", "--architecture"):
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arch_name = arg
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arch_name = arg
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elif opt in ("-e", "--entity"):
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elif opt in ("-e", "--entity"):
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entity_name = arg
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entity_name = arg
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elif opt in ("-n", "--name"):
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proj_name = arg
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elif opt in ("-i", "--indent"):
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elif opt in ("-i", "--indent"):
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indent = int(arg)
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indent = int(arg)
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elif opt in ("-t", "--log_trigger"):
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elif opt in ("-t", "--log_trigger"):
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log_trigger_addr = "X\"%08X\"" % (int(arg,16))
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log_trigger_addr = "X\"%08X\"" % (int(arg,16))
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elif opt in ("-s", "--sim_len"):
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elif opt in ("-s", "--sim_len"):
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| Line 243... |
Line 252... |
code_table_size < 0 or data_table_size<0:
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code_table_size < 0 or data_table_size<0:
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print "Some mandatory parameter is missing\n"
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print "Some mandatory parameter is missing\n"
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usage()
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usage()
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sys.exit(2)
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sys.exit(2)
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# Once all cmd line argumets are parsed, build secondary stuff out of them.
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# Contents of 1st vhdl comment line
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fileinfo = "File built automatically for project '" + proj_name + \
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"' by bin2hdl.py" # + \
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#str(datetime.datetime.now().strftime("%Y-%m-%d %H:%M"))
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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# Read BRAM initialization file, if any
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# Read BRAM initialization file, if any
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try:
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try:
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fin = open(code_filename, "rb")
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fin = open(code_filename, "rb")
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code = fin.read()
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code = fin.read()
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| Line 336... |
Line 352... |
"@data0@","@data1@","@data2@","@data3@",
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"@data0@","@data1@","@data2@","@data3@",
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"@data31@", "@data20@",
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"@data31@", "@data20@",
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"@data-32bit@",
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"@data-32bit@",
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"@flash@",
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"@flash@",
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"@entity_name@","@arch_name@",
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"@entity_name@","@arch_name@",
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"@fileinfo@",
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"@sim_len@",
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"@sim_len@",
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"@xram_size@",
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"@xram_size@",
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"@code_table_size@","@code_addr_size@",
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"@code_table_size@","@code_addr_size@",
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"@data_table_size@","@data_addr_size@",
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"@data_table_size@","@data_addr_size@",
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"@prom_size@",
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"@prom_size@",
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"@log_trigger_addr@"];
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"@log_trigger_addr@"];
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replacement = vhdl_code_strings + vhdl_data_strings + \
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replacement = vhdl_code_strings + vhdl_data_strings + \
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[vhdl_flash_string,
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[vhdl_flash_string,
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entity_name, arch_name,
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entity_name, arch_name,
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fileinfo,
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str(simulation_length),
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str(simulation_length),
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str(data_table_size),
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str(data_table_size),
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str(code_table_size),
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str(code_table_size),
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str(int(math.floor(math.log(code_table_size,2)))),
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str(int(math.floor(math.log(code_table_size,2)))),
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str(data_table_size),
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str(data_table_size),
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