| Line 19... |
Line 19... |
print "{o|output} <filename> Target VHDL file name"
|
print "{o|output} <filename> Target VHDL file name"
|
print "code_size <number> Size of code memory in words (decimal)"
|
print "code_size <number> Size of code memory in words (decimal)"
|
print "data_size <number> Size of data memory in words (decimal)"
|
print "data_size <number> Size of data memory in words (decimal)"
|
print ""
|
print ""
|
print "Additionally, any of these arguments can be given:"
|
print "Additionally, any of these arguments can be given:"
|
|
print "{s|sim_len} <number> Length of simulation in clock cycles"
|
print "{d|data} <filename> Data binary image file name"
|
print "{d|data} <filename> Data binary image file name"
|
print "{h|help} Display some help text and exit"
|
print "{h|help} Display some help text and exit"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
|
|
def help():
|
def help():
|
| Line 33... |
Line 34... |
print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
|
print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
|
print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
|
print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
|
print "Other template tags are replaced as follows:"
|
print "Other template tags are replaced as follows:"
|
print "@entity_name@ : Name of entity in target vhdl file"
|
print "@entity_name@ : Name of entity in target vhdl file"
|
print "@arch_name@ : Name of architecture in target vhdl file"
|
print "@arch_name@ : Name of architecture in target vhdl file"
|
|
print "@sim_len@ : Length of simulation in clock cycles"
|
print "@code_table_size@ : Size of code RAM block, in words"
|
print "@code_table_size@ : Size of code RAM block, in words"
|
print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
|
print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
|
print "@data_table_size@ : Size of data RAM block, in words"
|
print "@data_table_size@ : Size of data RAM block, in words"
|
print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
|
print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
|
|
|
| Line 89... |
Line 91... |
target_filename = "tb.vhdl" # name of target vhdl file
|
target_filename = "tb.vhdl" # name of target vhdl file
|
indent = 4 # indentation for table data, in spaces
|
indent = 4 # indentation for table data, in spaces
|
code_table_size = -1 # size of VHDL table
|
code_table_size = -1 # size of VHDL table
|
data_table_size = -1 # size of VHDL table
|
data_table_size = -1 # size of VHDL table
|
bin_words = 0 # size of binary file in 32-bit words
|
bin_words = 0 # size of binary file in 32-bit words
|
|
simulation_length = 22000 # length of logic simulation in clock cycles
|
|
|
#
|
#
|
|
|
try:
|
try:
|
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:",
|
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:",
|
["help", "code=", "data=", "vhdl=", "architecture=",
|
["help", "code=", "data=", "vhdl=", "architecture=",
|
"entity=", "output=", "indent=", "code_size=", "data_size="])
|
"entity=", "output=", "indent=", "sim_len=",
|
|
"code_size=", "data_size="])
|
except getopt.GetoptError:
|
except getopt.GetoptError:
|
usage()
|
usage()
|
sys.exit(2)
|
sys.exit(2)
|
|
|
# Parse coommand line parameters
|
# Parse coommand line parameters
|
| Line 120... |
Line 124... |
arch_name = arg
|
arch_name = arg
|
elif opt in ("-e", "--entity"):
|
elif opt in ("-e", "--entity"):
|
entity_name = arg
|
entity_name = arg
|
elif opt in ("-i", "--indent"):
|
elif opt in ("-i", "--indent"):
|
indent = int(arg)
|
indent = int(arg)
|
|
elif opt in ("-s", "--sim_len"):
|
|
simulation_length = int(arg)
|
elif opt == "--code_size":
|
elif opt == "--code_size":
|
code_table_size = int(arg)
|
code_table_size = int(arg)
|
elif opt == "--data_size":
|
elif opt == "--data_size":
|
data_table_size = int(arg)
|
data_table_size = int(arg)
|
|
|
| Line 186... |
Line 192... |
|
|
# ...and build the keyword and replacement tables
|
# ...and build the keyword and replacement tables
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
"@data0@","@data1@","@data2@","@data3@",
|
"@data0@","@data1@","@data2@","@data3@",
|
"@entity_name@","@arch_name@",
|
"@entity_name@","@arch_name@",
|
|
"@sim_len@",
|
"@code_table_size@","@code_addr_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@data_table_size@","@data_addr_size@"];
|
"@data_table_size@","@data_addr_size@"];
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
[entity_name, arch_name,
|
[entity_name, arch_name,
|
|
str(simulation_length),
|
str(code_table_size),
|
str(code_table_size),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(data_table_size),
|
str(data_table_size),
|
str(int(math.floor(math.log(data_table_size,2))))]
|
str(int(math.floor(math.log(data_table_size,2))))]
|
|
|
