| Line 20... |
Line 20... |
print "code_size <number> Size of code memory in words (decimal)"
|
print "code_size <number> Size of code memory in words (decimal)"
|
print "data_size <number> Size of data memory in words (decimal)"
|
print "data_size <number> Size of data memory in words (decimal)"
|
print ""
|
print ""
|
print "Additionally, any of these arguments can be given:"
|
print "Additionally, any of these arguments can be given:"
|
print "{s|sim_len} <number> Length of simulation in clock cycles"
|
print "{s|sim_len} <number> Length of simulation in clock cycles"
|
print "{d|data} <filename> Data binary image file name"
|
print "{d|data} <filename> Data binary image file name or 'empty'"
|
print "{h|help} Display some help text and exit"
|
print "{h|help} Display some help text and exit"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
|
|
def help():
|
def help():
|
print "\nPurpose:\n"
|
print "\nPurpose:\n"
|
print "Reads the code and data binary files and 'slices' them in byte"
|
print "Reads the code and data binary files and 'slices' them in byte"
|
print "columns."
|
print "columns."
|
print "The data columns are converted to VHDL strings and then inserted"
|
print "The data columns are converted to VHDL strings and then inserted"
|
print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
|
print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
|
print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
|
print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
|
|
print "Tags like @data31@ and @data20@ etc. can be used to initialize"
|
|
print "memories in 16-bit buses, also split in byte columns.\n"
|
print "Other template tags are replaced as follows:"
|
print "Other template tags are replaced as follows:"
|
print "@entity_name@ : Name of entity in target vhdl file"
|
print "@entity_name@ : Name of entity in target vhdl file"
|
print "@arch_name@ : Name of architecture in target vhdl file"
|
print "@arch_name@ : Name of architecture in target vhdl file"
|
print "@sim_len@ : Length of simulation in clock cycles"
|
print "@sim_len@ : Length of simulation in clock cycles"
|
print "@code_table_size@ : Size of code RAM block, in words"
|
print "@code_table_size@ : Size of code RAM block, in words"
|
| Line 61... |
Line 63... |
byte = 0
|
byte = 0
|
index = index + 1
|
index = index + 1
|
|
|
# Write the data for each of the four column tables as a VHDL byte
|
# Write the data for each of the four column tables as a VHDL byte
|
# constant table.
|
# constant table.
|
vhdl_data_strings = [" "*indent_size]*4
|
vhdl_data_strings = [" "*indent_size]*6
|
|
|
for j in range(4):
|
for j in range(4):
|
col = 0
|
col = 0
|
word = len(tables[j])
|
word = len(tables[j])
|
for c in tables[j]:
|
for c in tables[j]:
|
| Line 77... |
Line 79... |
col = col + 1
|
col = col + 1
|
if col == 8:
|
if col == 8:
|
col = 0
|
col = 0
|
item = item + "\n" + " "*indent_size
|
item = item + "\n" + " "*indent_size
|
vhdl_data_strings[j] = vhdl_data_strings[j] + item
|
vhdl_data_strings[j] = vhdl_data_strings[j] + item
|
|
vhdl_data_strings[j] = "\n" + vhdl_data_strings[j]
|
|
|
|
# ok, now build init strings for 16-bit wide memorier, split in 2 byte
|
|
# columns: an odd column with bytes 3:1 and an even column with bytes 2:0
|
|
byte_order = [3,1,2,0]
|
|
for j in range(2):
|
|
col = 0
|
|
word_count = len(tables[j*2])
|
|
for i in range(word_count):
|
|
w_high = tables[byte_order[j*2+0]][i]
|
|
w_low = tables[byte_order[j*2+1]][i]
|
|
word_count = word_count - 1
|
|
if word_count > 0:
|
|
item_h = "X\"%02X\"," % w_high
|
|
item_l = "X\"%02X\"," % w_low
|
|
else:
|
|
item_h = "X\"%02X\"," % w_high
|
|
item_l = "X\"%02X\"" % w_low
|
|
item = item_h + item_l
|
|
col = col + 1
|
|
if col == 4:
|
|
col = 0
|
|
item = item + "\n" + " "*indent_size
|
|
vhdl_data_strings[4+j] = vhdl_data_strings[4+j] + item
|
|
vhdl_data_strings[4+j] = "\n" + vhdl_data_strings[4+j]
|
|
|
return vhdl_data_strings
|
return vhdl_data_strings
|
|
|
def main(argv):
|
def main(argv):
|
code_filename = "" # file with code sections (text+reginfo+rodata)
|
code_filename = "" # file with code sections (text+reginfo+rodata)
|
| Line 134... |
Line 161... |
data_table_size = int(arg)
|
data_table_size = int(arg)
|
|
|
# See if all mandatory options are there
|
# See if all mandatory options are there
|
if code_filename=="" or vhdl_filename=="" or \
|
if code_filename=="" or vhdl_filename=="" or \
|
code_table_size < 0 or data_table_size<0:
|
code_table_size < 0 or data_table_size<0:
|
|
print "Some mandatory parameter is missing\n"
|
usage()
|
usage()
|
sys.exit(2)
|
sys.exit(2)
|
|
|
|
|
# Open binary code and data input files and read them into buffers
|
# Open binary code and data input files and read them into buffers
|
| Line 147... |
Line 175... |
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % code_filename
|
print "Binary File %s not found" % code_filename
|
|
|
if data_filename != "":
|
if data_filename != "":
|
|
if data_filename == "empty":
|
|
data = []
|
|
else:
|
try:
|
try:
|
fin = open(data_filename, "rb")
|
fin = open(data_filename, "rb")
|
data = fin.read()
|
data = fin.read()
|
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
| Line 179... |
Line 210... |
if data_filename != "":
|
if data_filename != "":
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
else:
|
else:
|
# In case we didn't get a data binary, we want the vhdl compilation
|
# In case we didn't get a data binary, we want the vhdl compilation
|
# to fail when @data@ tags are used, just to catch the error
|
# to fail when @data@ tags are used, just to catch the error
|
vhdl_data_strings = ["error: missing data binary file"]*4
|
vhdl_data_strings = ["error: missing data binary file"]*6
|
|
|
# Now start scanning the VHDL template, inserting data where needed
|
# Now start scanning the VHDL template, inserting data where needed
|
|
|
# Read template file...
|
# Read template file...
|
fin = open(vhdl_filename, "r")
|
fin = open(vhdl_filename, "r")
|
vhdl_lines = fin.readlines()
|
vhdl_lines = fin.readlines()
|
fin.close()
|
fin.close()
|
|
|
# ...and build the keyword and replacement tables
|
# ...and build the keyword and replacement tables
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
|
"@code31@", "@code20@",
|
"@data0@","@data1@","@data2@","@data3@",
|
"@data0@","@data1@","@data2@","@data3@",
|
|
"@data31@", "@data20@",
|
"@entity_name@","@arch_name@",
|
"@entity_name@","@arch_name@",
|
"@sim_len@",
|
"@sim_len@",
|
|
"@xram_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@data_table_size@","@data_addr_size@"];
|
"@data_table_size@","@data_addr_size@"];
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
[entity_name, arch_name,
|
[entity_name, arch_name,
|
str(simulation_length),
|
str(simulation_length),
|
|
str(data_table_size),
|
str(code_table_size),
|
str(code_table_size),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(data_table_size),
|
str(data_table_size),
|
str(int(math.floor(math.log(data_table_size,2))))]
|
str(int(math.floor(math.log(data_table_size,2))))]
|
|
|
