| Line 6... |
Line 6... |
import getopt
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import getopt
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import math
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import math
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def usage():
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def usage():
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print ""
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print "usage:"
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print "usage:"
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print "python bin2hdl.py [arguments]\n"
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print "python bin2hdl.py [arguments]\n"
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print "Inserts data in VHDL template\n"
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print "Inserts data in VHDL template\n"
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print "ALL of the following arguments should be given, in any order:"
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print "ALL of the following arguments should be given, in any order:"
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print "{c|code} <filename> Code binary image file name"
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print "{c|code} <filename> Code binary image file name"
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print "{v|vhdl} <filename> VHDL template"
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print "{v|vhdl} <filename> VHDL template"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{o|output} <filename> Target VHDL file name"
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print "{o|output} <filename> Target VHDL file name"
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print "code_size <number> Size of code memory in words (decimal)"
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print "code_size <number> Size of bram memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "flash_size <number> Size of flash memory in words (decimal)"
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print "(note the flash and xram info are used in simulation only)"
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print ""
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print ""
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print "Additionally, any of these arguments can be given:"
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print "Additionally, any of these arguments can be given:"
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print "{s|sim_len} <number> Length of simulation in clock cycles"
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print "{s|sim_len} <number> Length of simulation in clock cycles"
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print "{d|data} <filename> Data binary image file name or 'empty'"
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print "{d|data} <filename> Data binary image file name or 'empty'"
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print "{h|help} Display some help text and exit"
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print "{h|help} Display some help text and exit"
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| Line 43... |
Line 46... |
print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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def build_vhdl_flash_table(flash, table_size, indent_size):
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# Build vhdl table for flash data
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# fill up empty table space with zeros
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if len(flash) < table_size*4:
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flash = flash + '\0'*4*(table_size-len(flash)/4)
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num_words = len(flash)/4
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remaining = num_words;
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col = 0
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vhdl_flash_string = "\n" + " "*indent_size
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for w in range(num_words):
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b0 = ord(flash[w*4+0]);
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b1 = ord(flash[w*4+1]);
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b2 = ord(flash[w*4+2]);
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b3 = ord(flash[w*4+3]);
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if remaining > 1:
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item = "X\"%02X%02X%02X%02X\"," % (b0, b1, b2, b3)
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else:
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item = "X\"%02X%02X%02X%02X\"" % (b0, b1, b2, b3)
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remaining = remaining - 1
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col = col + 1
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if col == 4:
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col = 0
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item = item + "\n" + " "*indent_size
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vhdl_flash_string = vhdl_flash_string + item
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return vhdl_flash_string
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def build_vhdl_tables(code,table_size, indent_size):
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def build_vhdl_tables(code,table_size, indent_size):
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# Build the four byte column tables. [0] is LSB, [3] is MSB
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# Build the four byte column tables. [0] is LSB, [3] is MSB
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# Useful only for BRAM and SRAM tables
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tables = [[0 for i in range(table_size)] for i in range(4)]
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tables = [[0 for i in range(table_size)] for i in range(4)]
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# Separate binary data into byte columns
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# Separate binary data into byte columns
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# (here's where data endianess matters, we're assuming big endian)
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# (here's where data endianess matters, we're assuming big endian)
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byte = 0 # byte 0 is LSB, 3 is MSB
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byte = 0 # byte 0 is LSB, 3 is MSB
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| Line 134... |
Line 172... |
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return vhdl_data_strings
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return vhdl_data_strings
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def main(argv):
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def main(argv):
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code_filename = "" # file with code sections (text+reginfo+rodata)
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code_filename = "" # file with bram contents ('code')
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data_filename = "" # file with data sections (data+bss)
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data_filename = "" # file with xram contents ('data')
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flash_filename = "" # file with flash contents ('flash')
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vhdl_filename = "" # name of vhdl template file
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vhdl_filename = "" # name of vhdl template file
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entity_name = "mips_tb" # name of vhdl entity to be generated
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entity_name = "mips_tb" # name of vhdl entity to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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target_filename = "tb.vhdl" # name of target vhdl file
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target_filename = "tb.vhdl" # name of target vhdl file
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indent = 4 # indentation for table data, in spaces
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indent = 4 # indentation for table data, in spaces
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code_table_size = -1 # size of VHDL table
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code_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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flash_table_size = 32; # default size of flash table in 32-bit words
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flash = ['\0']*4*flash_table_size # default simulated flash
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bin_words = 0 # size of binary file in 32-bit words
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bin_words = 0 # size of binary file in 32-bit words
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simulation_length = 22000 # length of logic simulation in clock cycles
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simulation_length = 22000 # length of logic simulation in clock cycles
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#
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#
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try:
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try:
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:",
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:",
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["help", "code=", "data=", "vhdl=", "architecture=",
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["help", "code=", "data=", "vhdl=", "architecture=",
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"entity=", "output=", "indent=", "sim_len=",
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"entity=", "output=", "indent=", "sim_len=", "flash=",
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"code_size=", "data_size="])
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"code_size=", "data_size=", "flash_size="])
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except getopt.GetoptError:
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except getopt.GetoptError, err:
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print ""
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print err
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usage()
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usage()
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sys.exit(2)
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sys.exit(2)
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# Parse coommand line parameters
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# Parse coommand line parameters
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for opt, arg in opts:
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for opt, arg in opts:
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| Line 171... |
Line 214... |
target_filename = arg
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target_filename = arg
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elif opt in ("-c", "--code"):
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elif opt in ("-c", "--code"):
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code_filename = arg
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code_filename = arg
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elif opt in ("-d", "--data"):
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elif opt in ("-d", "--data"):
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data_filename = arg
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data_filename = arg
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elif opt in ("-f", "--flash"):
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flash_filename = arg
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elif opt in ("-a", "--architecture"):
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elif opt in ("-a", "--architecture"):
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arch_name = arg
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arch_name = arg
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elif opt in ("-e", "--entity"):
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elif opt in ("-e", "--entity"):
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entity_name = arg
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entity_name = arg
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elif opt in ("-i", "--indent"):
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elif opt in ("-i", "--indent"):
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| Line 183... |
Line 228... |
simulation_length = int(arg)
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simulation_length = int(arg)
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elif opt == "--code_size":
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elif opt == "--code_size":
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code_table_size = int(arg)
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code_table_size = int(arg)
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elif opt == "--data_size":
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elif opt == "--data_size":
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data_table_size = int(arg)
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data_table_size = int(arg)
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elif opt == "--flash_size":
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flash_table_size = int(arg)
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# See if all mandatory options are there
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# See if all mandatory options are there
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if code_filename=="" or vhdl_filename=="" or \
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if code_filename=="" or vhdl_filename=="" or \
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code_table_size < 0 or data_table_size<0:
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code_table_size < 0 or data_table_size<0:
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print "Some mandatory parameter is missing\n"
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print "Some mandatory parameter is missing\n"
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| Line 211... |
Line 258... |
data = fin.read()
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data = fin.read()
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fin.close()
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fin.close()
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except IOError:
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except IOError:
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print "Binary File %s not found" % data_filename
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print "Binary File %s not found" % data_filename
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if flash_filename != "":
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if flash_filename == "empty":
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flash = [0]*flash_table_size
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else:
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try:
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fin = open(flash_filename, "rb")
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flash = fin.read()
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fin.close()
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except IOError:
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print "Binary File %s not found" % flash_filename
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#print "Read " + str(len(code)) + " bytes."
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#print "Read " + str(len(code)) + " bytes."
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# Make sure the code and data will fit in the tables
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# Make sure the code and data will fit in the tables
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bin_words = len(code) / 4
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bin_words = len(code) / 4
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if bin_words > code_table_size:
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if bin_words > code_table_size:
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| Line 228... |
Line 286... |
if bin_words > data_table_size:
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if bin_words > data_table_size:
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print "Data does not fit table: " + str(bin_words) + " words,",
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print "Data does not fit table: " + str(bin_words) + " words,",
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print str(data_table_size) + " table entries"
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print str(data_table_size) + " table entries"
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sys.exit(1)
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sys.exit(1)
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if flash_filename != "":
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bin_words = len(flash) / 4
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if bin_words > flash_table_size:
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print "Flash data does not fit table: " + str(bin_words) + " words,",
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print str(flash_table_size) + " table entries"
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sys.exit(1)
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# Build the VHDL strings for each slice of both code and data tables
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# Build the VHDL strings for each slice of both code and data tables
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vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
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vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
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if data_filename != "":
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if data_filename != "":
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vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
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vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
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else:
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else:
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# In case we didn't get a data binary, we want the vhdl compilation
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# In case we didn't get a data binary, we want the vhdl compilation
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# to fail when @data@ tags are used, just to catch the error
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# to fail when @data@ tags are used, just to catch the error
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vhdl_data_strings = ["error: missing data binary file"]*6
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vhdl_data_strings = ["error: missing data binary file"]*6
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vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
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# Now start scanning the VHDL template, inserting data where needed
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# Now start scanning the VHDL template, inserting data where needed
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# Read template file...
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# Read template file...
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fin = open(vhdl_filename, "r")
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fin = open(vhdl_filename, "r")
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vhdl_lines = fin.readlines()
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vhdl_lines = fin.readlines()
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| Line 252... |
Line 319... |
"@code31@", "@code20@",
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"@code31@", "@code20@",
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"@code-32bit@",
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"@code-32bit@",
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"@data0@","@data1@","@data2@","@data3@",
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"@data0@","@data1@","@data2@","@data3@",
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"@data31@", "@data20@",
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"@data31@", "@data20@",
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"@data-32bit@",
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"@data-32bit@",
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"@flash@",
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"@entity_name@","@arch_name@",
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"@entity_name@","@arch_name@",
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"@sim_len@",
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"@sim_len@",
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"@xram_size@",
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"@xram_size@",
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"@code_table_size@","@code_addr_size@",
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"@code_table_size@","@code_addr_size@",
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"@data_table_size@","@data_addr_size@"];
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"@data_table_size@","@data_addr_size@",
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"@prom_size@"];
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replacement = vhdl_code_strings + vhdl_data_strings + \
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replacement = vhdl_code_strings + vhdl_data_strings + \
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[entity_name, arch_name,
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[vhdl_flash_string,
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entity_name, arch_name,
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str(simulation_length),
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str(simulation_length),
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str(data_table_size),
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str(data_table_size),
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str(code_table_size),
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str(code_table_size),
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str(int(math.floor(math.log(code_table_size,2)))),
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str(int(math.floor(math.log(code_table_size,2)))),
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str(data_table_size),
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str(data_table_size),
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str(int(math.floor(math.log(data_table_size,2))))]
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str(int(math.floor(math.log(data_table_size,2)))),
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str(flash_table_size)]
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# Now traverse the template lines replacing any keywords with the proper
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# Now traverse the template lines replacing any keywords with the proper
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# vhdl stuff we just built above.
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# vhdl stuff we just built above.
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output = ""
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output = ""
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for vhdl_line in vhdl_lines:
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for vhdl_line in vhdl_lines:
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