| Line 22... |
Line 22... |
print "data_size <number> Size of data memory in words (decimal)"
|
print "data_size <number> Size of data memory in words (decimal)"
|
print "flash_size <number> Size of flash memory in words (decimal)"
|
print "flash_size <number> Size of flash memory in words (decimal)"
|
print "(note the flash and xram info are used in simulation only)"
|
print "(note the flash and xram info are used in simulation only)"
|
print ""
|
print ""
|
print "Additionally, any of these arguments can be given:"
|
print "Additionally, any of these arguments can be given:"
|
|
print "{t|log_trigger} <number> Fetch address that triggers file logging"
|
print "{s|sim_len} <number> Length of simulation in clock cycles"
|
print "{s|sim_len} <number> Length of simulation in clock cycles"
|
print "{d|data} <filename> Data binary image file name or 'empty'"
|
print "{d|data} <filename> Data binary image file name or 'empty'"
|
print "{h|help} Display some help text and exit"
|
print "{h|help} Display some help text and exit"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
print "{i|indent} <number> Indentation in VHDL tables (decimal)"
|
|
|
| Line 183... |
Line 184... |
target_filename = "tb.vhdl" # name of target vhdl file
|
target_filename = "tb.vhdl" # name of target vhdl file
|
indent = 4 # indentation for table data, in spaces
|
indent = 4 # indentation for table data, in spaces
|
code_table_size = -1 # size of VHDL table
|
code_table_size = -1 # size of VHDL table
|
data_table_size = -1 # size of VHDL table
|
data_table_size = -1 # size of VHDL table
|
flash_table_size = 32; # default size of flash table in 32-bit words
|
flash_table_size = 32; # default size of flash table in 32-bit words
|
|
log_trigger_addr = "X\"FFFFFFFF\"" # default log trigger address
|
flash = ['\0']*4*flash_table_size # default simulated flash
|
flash = ['\0']*4*flash_table_size # default simulated flash
|
bin_words = 0 # size of binary file in 32-bit words
|
bin_words = 0 # size of binary file in 32-bit words
|
simulation_length = 22000 # length of logic simulation in clock cycles
|
simulation_length = 22000 # length of logic simulation in clock cycles
|
|
|
#
|
#
|
|
|
try:
|
try:
|
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:",
|
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
|
["help", "code=", "data=", "vhdl=", "architecture=",
|
["help", "code=", "data=", "vhdl=", "architecture=",
|
"entity=", "output=", "indent=", "sim_len=", "flash=",
|
"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
|
"code_size=", "data_size=", "flash_size="])
|
"code_size=", "data_size=", "flash_size="])
|
except getopt.GetoptError, err:
|
except getopt.GetoptError, err:
|
print ""
|
print ""
|
print err
|
print err
|
usage()
|
usage()
|
| Line 222... |
Line 224... |
arch_name = arg
|
arch_name = arg
|
elif opt in ("-e", "--entity"):
|
elif opt in ("-e", "--entity"):
|
entity_name = arg
|
entity_name = arg
|
elif opt in ("-i", "--indent"):
|
elif opt in ("-i", "--indent"):
|
indent = int(arg)
|
indent = int(arg)
|
|
elif opt in ("-t", "--log_trigger"):
|
|
log_trigger_addr = "X\"%08X\"" % (int(arg,16))
|
elif opt in ("-s", "--sim_len"):
|
elif opt in ("-s", "--sim_len"):
|
simulation_length = int(arg)
|
simulation_length = int(arg)
|
elif opt == "--code_size":
|
elif opt == "--code_size":
|
code_table_size = int(arg)
|
code_table_size = int(arg)
|
elif opt == "--data_size":
|
elif opt == "--data_size":
|
| Line 238... |
Line 242... |
code_table_size < 0 or data_table_size<0:
|
code_table_size < 0 or data_table_size<0:
|
print "Some mandatory parameter is missing\n"
|
print "Some mandatory parameter is missing\n"
|
usage()
|
usage()
|
sys.exit(2)
|
sys.exit(2)
|
|
|
|
#---------------------------------------------------------------------------
|
# Open binary code and data input files and read them into buffers
|
# Read BRAM initialization file, if any
|
try:
|
try:
|
fin = open(code_filename, "rb")
|
fin = open(code_filename, "rb")
|
code = fin.read()
|
code = fin.read()
|
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % code_filename
|
print "Binary File %s not found" % code_filename
|
|
|
|
# Make sure the code and data will fit in the tables
|
|
bin_words = len(code) / 4
|
|
if bin_words > code_table_size:
|
|
print "Code does not fit table: " + str(bin_words) + " words,",
|
|
print str(code_table_size) + " table entries"
|
|
sys.exit(1)
|
|
|
|
# Build the VHDL strings for each slice of the BRAM tables
|
|
vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
|
|
|
|
|
|
#---------------------------------------------------------------------------
|
|
# Read XRAM initialization file, if any.
|
if data_filename != "":
|
if data_filename != "":
|
if data_filename == "empty":
|
if data_filename == "empty":
|
data = []
|
data = []
|
else:
|
else:
|
try:
|
try:
|
| Line 258... |
Line 275... |
data = fin.read()
|
data = fin.read()
|
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % data_filename
|
print "Binary File %s not found" % data_filename
|
|
|
|
# FIXME We're not checking for BSS size here, only .data (?)
|
|
bin_words = len(data) / 4
|
|
if bin_words > data_table_size:
|
|
print "Data does not fit table: " + str(bin_words) + " words,",
|
|
print str(data_table_size) + " table entries"
|
|
sys.exit(1)
|
|
|
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
|
else:
|
|
# In case we didn't get a data binary, we will initialize any XRAM in
|
|
# the template with zeros
|
|
vhdl_data_strings = (["(others => X\"00\")"]*4) + \
|
|
(["(others => X\"00\")"]*2) + \
|
|
(["(others => X\"00000000\")"])
|
|
|
|
|
|
#---------------------------------------------------------------------------
|
|
# Read FLASH initialization file, if any
|
|
|
if flash_filename != "":
|
if flash_filename != "":
|
if flash_filename == "empty":
|
if flash_filename == "empty":
|
flash = [0]*flash_table_size
|
flash = [0]*flash_table_size
|
else:
|
else:
|
try:
|
try:
|
| Line 269... |
Line 305... |
flash = fin.read()
|
flash = fin.read()
|
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % flash_filename
|
print "Binary File %s not found" % flash_filename
|
|
|
#print "Read " + str(len(code)) + " bytes."
|
# make sure file will fit simulated FLASH size
|
|
|
# Make sure the code and data will fit in the tables
|
|
bin_words = len(code) / 4
|
|
if bin_words > code_table_size:
|
|
print "Code does not fit table: " + str(bin_words) + " words,",
|
|
print str(code_table_size) + " table entries"
|
|
sys.exit(1)
|
|
|
|
if data_filename != "":
|
|
# FIXME We're not checking for BSS size here, only .data (?)
|
|
bin_words = len(data) / 4
|
|
if bin_words > data_table_size:
|
|
print "Data does not fit table: " + str(bin_words) + " words,",
|
|
print str(data_table_size) + " table entries"
|
|
sys.exit(1)
|
|
|
|
if flash_filename != "":
|
|
bin_words = len(flash) / 4
|
bin_words = len(flash) / 4
|
if bin_words > flash_table_size:
|
if bin_words > flash_table_size:
|
print "Flash data does not fit table: " + str(bin_words) + " words,",
|
print "Flash data does not fit table: " + str(bin_words) + " words,",
|
print str(flash_table_size) + " table entries"
|
print str(flash_table_size) + " table entries"
|
sys.exit(1)
|
sys.exit(1)
|
|
|
|
|
# Build the VHDL strings for each slice of both code and data tables
|
# Build the VHDL strings for the simulated FLASH
|
vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
|
|
if data_filename != "":
|
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
|
else:
|
|
# In case we didn't get a data binary, we want the vhdl compilation
|
|
# to fail when @data@ tags are used, just to catch the error
|
|
vhdl_data_strings = ["error: missing data binary file"]*6
|
|
|
|
vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
|
vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
|
|
|
# Now start scanning the VHDL template, inserting data where needed
|
|
|
#===========================================================================
|
|
# OK, we just read all binary files and built all VHDL memory initialization
|
|
# strings. Now start scanning the VHDL template, inserting data where needed
|
|
|
# Read template file...
|
# Read template file...
|
fin = open(vhdl_filename, "r")
|
fin = open(vhdl_filename, "r")
|
vhdl_lines = fin.readlines()
|
vhdl_lines = fin.readlines()
|
fin.close()
|
fin.close()
|
| Line 325... |
Line 339... |
"@entity_name@","@arch_name@",
|
"@entity_name@","@arch_name@",
|
"@sim_len@",
|
"@sim_len@",
|
"@xram_size@",
|
"@xram_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@data_table_size@","@data_addr_size@",
|
"@data_table_size@","@data_addr_size@",
|
"@prom_size@"];
|
"@prom_size@",
|
|
"@log_trigger_addr@"];
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
[vhdl_flash_string,
|
[vhdl_flash_string,
|
entity_name, arch_name,
|
entity_name, arch_name,
|
str(simulation_length),
|
str(simulation_length),
|
str(data_table_size),
|
str(data_table_size),
|
str(code_table_size),
|
str(code_table_size),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(data_table_size),
|
str(data_table_size),
|
str(int(math.floor(math.log(data_table_size,2)))),
|
str(int(math.floor(math.log(data_table_size,2)))),
|
str(flash_table_size)]
|
str(flash_table_size),
|
|
log_trigger_addr]
|
|
|
# Now traverse the template lines replacing any keywords with the proper
|
# Now traverse the template lines replacing any keywords with the proper
|
# vhdl stuff we just built above.
|
# vhdl stuff we just built above.
|
output = ""
|
output = ""
|
for vhdl_line in vhdl_lines:
|
for vhdl_line in vhdl_lines:
|
