| Line 4... |
Line 4... |
# Operation:
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# Operation:
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# 1.- If the trapped opcode is one of the emulated opcodes, it is emulated.
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# 1.- If the trapped opcode is one of the emulated opcodes, it is emulated.
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# 2.- Otherwise, nothing is done (as if the trapped opcode was a NOP) and a flag
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# 2.- Otherwise, nothing is done (as if the trapped opcode was a NOP) and a flag
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# is set in the emu_frame area (meant for debugging, mostly).
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# is set in the emu_frame area (meant for debugging, mostly).
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# 3.- In either case, if the trapped opcode is in a jump delay slot, the jump
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# 3.- In either case, if the trapped opcode is in a jump delay slot, the jump
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# instruction is emulated. FIXME it isn't yet
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# instruction is emulated.
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# FIXME it isn't yet
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#
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#
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# Uses a small workspace in the BSS section. Does NOT use the regular stack
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# Uses a small workspace in the BSS section. Does NOT use the regular stack
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# nor makes any assumptions about any registers, including the sp.
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# nor makes any assumptions about any registers, including the sp.
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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| Line 48... |
Line 49... |
sw $t0,-24($k1)
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sw $t0,-24($k1)
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sw $t1,-28($k1)
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sw $t1,-28($k1)
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sw $t2,-32($k1)
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sw $t2,-32($k1)
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move $sp,$k1
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move $sp,$k1
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|
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# FIXME handle delay slot situation: emulate jump if necessary
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mfc0 $t0,$14 # get bad opcode (or branch opcode if in DS)
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# get bad opcode
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mfc0 $t0,$14
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lw $k0,0($t0)
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lw $k0,0($t0)
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# Handle delay slot situation: emulate jump if necessary
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mfc0 $k1,$13 # Check bit 31 (BD) from C0 cause register
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bltzal $k1,emulate_branch
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nop
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# decode instruction: either SPECIAL3 or SPECIAL2
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# decode instruction: either SPECIAL3 or SPECIAL2
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srl $t1,$k0,26
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srl $t1,$k0,26
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xori $t0,$t1,0x01f
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xori $t0,$t1,0x01f
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beqz $t0,mips32_special3
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beqz $t0,mips32_special3
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xori $t0,$t1,0x01c
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xori $t0,$t1,0x01c
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| Line 118... |
Line 122... |
li $t0,0x20010000 # Write ignored opcode to debug register
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li $t0,0x20010000 # Write ignored opcode to debug register
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sw $k0,1024($t0)
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sw $k0,1024($t0)
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j opcode_emu_return
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j opcode_emu_return
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nop
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nop
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|
|
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# Get the branch opcode, decode it and emulate it
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# entry: $k0 = opcode, $t0 = address of branch
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# exit: $k0 = opcode that triggered exception (in branch delay)
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emulate_branch:
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|
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# FIXME branch emulation is missing!
|
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lw $k0,4($t0) # read actual guilty opcode
|
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jr $ra
|
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nop
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#---- Branch emulation routines --------------------------------------------
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# FIXME branch emulation missing
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|
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#---- Opcode emulation routines --------------------------------------------
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#---- Opcode emulation routines --------------------------------------------
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|
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# CLZ: rd <- count leading zeros on rs
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# CLZ: rd <- count leading zeros on rs
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mips32_CLZ:
|
mips32_CLZ:
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jal get_source_register # $k1 = source register (Rs)
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jal get_source_register # $k1 = source register (Rs)
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