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#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
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#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
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#-- Create VHDL file for simulation test bench using TB2 template
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#-- Create VHDL package with data and parameters for simulation
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sim: hello demo
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sim: hello demo
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$(TO_VHDL) --code hello.code --data hello.data \
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$(VHDL_OBJ_PKG) --project="Hello World" \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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--package sim_params_pkg \
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--log_trigger=0xbfc00000 \
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--bin hello.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb2_template.vhdl \
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--bin hello.data --name sram_init --xram_size $(XRAM_SIZE)\
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-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2
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--name prom_init --flash_size 0 \
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$(TO_VHDL) --code hello.code --data hello.data \
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--output $(TB_DIR)/sim_params_pkg.vhdl \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \
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--log_trigger=0xbfc00000 \
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-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \
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-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2
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#-- Create VHDL file for simulation test bench using TB0 template
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#-- Create VHDL file for simulation test bench using TB0 template
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#-- This will instantiate the CPU without any caches or memory controller and
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#-- will run the program off of an initialized ROM connected to the code
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#-- interface.
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#-- NOTE: This target has not been used in some time and may be broken. It's
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#-- here because it can still be useful in an emergency.
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sim_bram: hello
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sim_bram: hello
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$(TO_VHDL) --code hello.code --data hello.data \
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$(TO_VHDL) --code hello.code --data hello.data \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb0_template.vhdl \
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-s $(SIM_LENGTH) -v $(SRC_DIR)/mips_tb0_template.vhdl \
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-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2
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-o $(TB_DIR)/mips_tb2.vhdl -e mips_tb2
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#-- Create VHDL file for hardware demo
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#-- Create VHDL package with data and parameters for simulation and syntesis
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demo: hello
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demo: hello
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$(TO_VHDL) --code hello.code --data hello.data \
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$(VHDL_OBJ_PKG) --project="Hello World" \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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--package obj_code_pkg \
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-v $(SRC_DIR)/code_rom_template.vhdl -n "Hello World" \
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--bin hello.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
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-o $(DEMO_DIR)/code_rom_pkg.vhdl
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--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl
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#-- And now the usual housekeeping stuff ---------------------------------------
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#-- And now the usual housekeeping stuff ---------------------------------------
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.PHONY: clean
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.PHONY: clean
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