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include ../common/makefile
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include ../common/makefile
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# We'll run the simulation for long enough to complete the test
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# We'll run the simulation for long enough to complete the test
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SIM_LENGTH = 400000
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SIM_LENGTH = 400000
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# FPGA Block RAM parameters
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# FPGA Block RAM parameters (size in words)
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BRAM_START = 0xbfc00000
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BRAM_START = 0xbfc00000
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CODE_BRAM_SIZE = 2048
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CODE_BRAM_SIZE = 2048
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# Simulated FLASH parameters (size in bytes)
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FLASH_START = 0xb0000000
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FLASH_START = 0xb0000000
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# External RAM parameters (size in words)
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FLASH_SIZE = 4096
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XRAM_SIZE = 1024
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# External RAM parameters (size in 16-bit halfwords)
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# This is the RAM size simulated by slite; set the same value so the execution
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# logs match.
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XRAM_SIZE = 2048
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XRAM_START = 0x00000000
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XRAM_START = 0x00000000
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# Set to > 0 to initialize and enable the cache before running the tests
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# Set to > 0 to initialize and enable the cache before running the tests
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TEST_CACHE = 1
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TEST_CACHE = 1
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LFLAGS = -Ttext $(BRAM_START) -Tdata $(XRAM_START) -eentry -I elf32-big
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LFLAGS = -Ttext $(BRAM_START) -Tdata $(XRAM_START) -eentry -I elf32-big
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#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
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#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
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# Create VHDL file for simulation test bench using TB2 template
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#-- Create VHDL package with data and parameters for simulation
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sim: memtest demo
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sim: memtest demo
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$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \
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$(VHDL_OBJ_PKG) --project="Memtest" \
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--flash flash.bin --flash_size 4096 \
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--package sim_params_pkg \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
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--bin memtest.data --name sram_init --xram_size $(XRAM_SIZE) \
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-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2
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--bin flash.bin --name prom_init --flash_size $(FLASH_SIZE) \
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$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xbfc00000 \
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--output $(TB_DIR)/sim_params_pkg.vhdl \
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--flash flash.bin --flash_size 4096 \
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-s $(SIM_LENGTH) --log_trigger=0xbfc00000 \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)/sim_params_template.vhdl \
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-o $(TB_DIR)/sim_params_pkg.vhdl -e mips_tb2
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# Create VHDL file for hardware demo
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#-- Create VHDL package with data and parameters for syntesis
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demo: memtest
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demo: memtest
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$(TO_VHDL) --code memtest.code --data memtest.data --log_trigger=0xb0000000 \
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$(VHDL_OBJ_PKG) --project="Memtest" \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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--package obj_code_pkg \
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-v $(SRC_DIR)/code_rom_template.vhdl -n "Memory test" \
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--bin memtest.code --name obj_code --bram_size $(CODE_BRAM_SIZE) \
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-o $(DEMO_DIR)/code_rom_pkg.vhdl
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--output $(DEMO_DIR)/../SoC/bootstrap_code_pkg.vhdl
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#-- And now the usual housekeeping stuff ---------------------------------------
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#-- And now the usual housekeeping stuff ---------------------------------------
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.PHONY: clean
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.PHONY: clean
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