| Line 39... |
Line 39... |
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#---- UART stuff
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#---- UART stuff
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.set UART_BASE, 0x20000000 # UART base address
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.set UART_BASE, 0x20000000 # UART base address
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.set UART_TX, 0x0000 # TX reg offset
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.set UART_TX, 0x0000 # TX reg offset
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.set UART_STATUS, 0x0020 # status reg offset
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.set UART_STATUS, 0x0004 # status reg offset
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.set UART_TX_RDY, 0x0001 # tx ready flag mask
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#---- Debug register block -- 4 read-write, 32-bit registers
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#---- Debug register block -- 4 read-write, 32-bit registers
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.set DEBUG_BASE, 0x2000f000 # Debug block base
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.set DEBUG_BASE, 0x20010020 # Debug block base
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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.text
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.text
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.align 2
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.align 2
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| Line 394... |
Line 395... |
inv_i_cache_loop:
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inv_i_cache_loop:
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sw $a2,0($a0)
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sw $a2,0($a0)
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blt $a2,$a1,inv_i_cache_loop
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blt $a2,$a1,inv_i_cache_loop
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addi $a2,1
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addi $a2,1
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# Now, the D-Cache is different. To invalidate a D-Cache line you just
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# read from it (by proper selection of a dummy target address) while bits
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# CP0[12].17:16=01. The data read is undefined and should be discarded.
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li $a0,0 # Use any base address that is mapped
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li $a2,0
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li $a1,DCACHE_NUM_LINES-1
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inv_d_cache_loop:
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lw $zero,0($a0)
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addi $a0,DCACHE_LINE_SIZE*4
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blt $a2,$a1,inv_d_cache_loop
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addi $a2,1
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lui $a1,0x0002 # Leave with cache enabled
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mfc0 $a0,$12
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mfc0 $a0,$12
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li $a1,0x00020000 # Leave cache enabled
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andi $a0,$a0,0xffff
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or $a0,$a0,$a1
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or $a1,$a0,$a1
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jr $ra
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jr $ra
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mtc0 $a0,$12
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mtc0 $a1,$12
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#--- Special functions that do not use any RAM ---------------------------------
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#--- Special functions that do not use any RAM ---------------------------------
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# WARNING: Not for general use!
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# WARNING: Not for general use!
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| Line 418... |
Line 434... |
lb $v0,0($a0)
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lb $v0,0($a0)
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beqz $v0,puts_end
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beqz $v0,puts_end
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addiu $a0,1
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addiu $a0,1
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puts_wait_tx_rdy:
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puts_wait_tx_rdy:
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lw $v1,UART_STATUS($a2)
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lw $v1,UART_STATUS($a2)
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andi $v1,$v1,0x02
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andi $v1,$v1,UART_TX_RDY
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beqz $v1,puts_wait_tx_rdy
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beqz $v1,puts_wait_tx_rdy
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nop
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nop
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sw $v0,UART_TX($a2)
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sw $v0,UART_TX($a2)
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b puts_loop
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b puts_loop
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nop
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nop
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| Line 444... |
Line 460... |
andi $v0,$v0,0x0f
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andi $v0,$v0,0x0f
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addu $s2,$a3,$v0
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addu $s2,$a3,$v0
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lb $v0,0($s2)
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lb $v0,0($s2)
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put_hex_wait_tx_rdy:
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put_hex_wait_tx_rdy:
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lw $v1,UART_STATUS($a2)
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lw $v1,UART_STATUS($a2)
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andi $v1,$v1,0x02
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andi $v1,$v1,UART_TX_RDY
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beqz $v1,put_hex_wait_tx_rdy
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beqz $v1,put_hex_wait_tx_rdy
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nop
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nop
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sw $v0,UART_TX($a2)
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sw $v0,UART_TX($a2)
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bnez $a1,put_hex_loop
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bnez $a1,put_hex_loop
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