| Line 64... |
Line 64... |
.endif
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.endif
|
|
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#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
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start_test:
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start_test:
|
mtc0 $0,$12 # disable interrupts
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li $a0,0x00000002
|
|
mtc0 $a0,$12 # disable interrupts and cache
|
|
|
.ifdef TEST_CACHE # if we're going to test the I-caches then
|
.ifdef TEST_CACHE # if we're going to test the I-caches then
|
jal init_cache # invalidate all the I-Cache lines now
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jal init_cache # invalidate all the I-Cache lines now
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nop
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nop
|
.endif
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.endif
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| Line 321... |
Line 322... |
#---- Cache-related functions --------------------------------------------------
|
#---- Cache-related functions --------------------------------------------------
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|
|
# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)
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# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)
|
init_cache:
|
init_cache:
|
li $a0,0x00010000 # Disable cache, enable I-cache line invalidation
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li $a0,0x00010000 # Disable cache, enable I-cache line invalidation
|
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mfc0 $a1,$12
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|
or $a0,$a0,$a1
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mtc0 $a0,$12
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mtc0 $a0,$12
|
|
|
# In order to invalidate a I-Cache line we have to write its tag number to
|
# In order to invalidate a I-Cache line we have to write its tag number to
|
# any address while bits CP0[12].17:16=01. The write will be executed as a
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# any address while bits CP0[12].17:16=01. The write will be executed as a
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# regular write too, as a side effect, so we need to choose a harmless
|
# regular write too, as a side effect, so we need to choose a harmless
|
| Line 339... |
Line 342... |
blt $a2,$a1,inv_i_cache_loop
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blt $a2,$a1,inv_i_cache_loop
|
addi $a2,1
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addi $a2,1
|
|
|
mfc0 $a0,$12
|
mfc0 $a0,$12
|
li $a1,0x00020000 # Leave cache enabled
|
li $a1,0x00020000 # Leave cache enabled
|
or $a0,$a1,$a1
|
or $a0,$a0,$a1
|
jr $ra
|
jr $ra
|
mtc0 $a0,$12
|
mtc0 $a0,$12
|
|
|
|
|
|
|
