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[/] [ion/] [trunk/] [src/] [memtest/] [memtest.s] - Diff between revs 213 and 229

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Rev 213 Rev 229
Line 39... Line 39...
 
 
 
 
    #---- UART stuff
    #---- UART stuff
    .set UART_BASE,     0x20000000          # UART base address
    .set UART_BASE,     0x20000000          # UART base address
    .set UART_TX,       0x0000              # TX reg offset
    .set UART_TX,       0x0000              # TX reg offset
    .set UART_STATUS,   0x0020              # status reg offset
    .set UART_STATUS,   0x0004              # status reg offset
 
    .set UART_TX_RDY,   0x0001              # tx ready flag mask
 
 
    #---- Debug register block -- 4 read-write, 32-bit registers
    #---- Debug register block -- 4 read-write, 32-bit registers
    .set DEBUG_BASE,    0x2000f000          # Debug block base
    .set DEBUG_BASE,    0x20010020          # Debug block base
 
 
    #---------------------------------------------------------------------------
    #---------------------------------------------------------------------------
 
 
    .text
    .text
    .align  2
    .align  2
Line 394... Line 395...
inv_i_cache_loop:
inv_i_cache_loop:
    sw      $a2,0($a0)
    sw      $a2,0($a0)
    blt     $a2,$a1,inv_i_cache_loop
    blt     $a2,$a1,inv_i_cache_loop
    addi    $a2,1
    addi    $a2,1
 
 
 
    # Now, the D-Cache is different. To invalidate a D-Cache line you just
 
    # read from it (by proper selection of a dummy target address)  while bits
 
    # CP0[12].17:16=01. The data read is undefined and should be discarded.
 
 
 
    li      $a0,0               # Use any base address that is mapped
 
    li      $a2,0
 
    li      $a1,DCACHE_NUM_LINES-1
 
 
 
inv_d_cache_loop:
 
    lw      $zero,0($a0)
 
    addi    $a0,DCACHE_LINE_SIZE*4
 
    blt     $a2,$a1,inv_d_cache_loop
 
    addi    $a2,1
 
 
 
    lui     $a1,0x0002          # Leave with cache enabled
    mfc0    $a0,$12
    mfc0    $a0,$12
    li      $a1,0x00020000      # Leave cache enabled
    andi    $a0,$a0,0xffff
    or      $a0,$a0,$a1
    or      $a1,$a0,$a1
    jr      $ra
    jr      $ra
    mtc0    $a0,$12
    mtc0    $a1,$12
 
 
 
 
 
 
#--- Special functions that do not use any RAM ---------------------------------
#--- Special functions that do not use any RAM ---------------------------------
# WARNING: Not for general use!
# WARNING: Not for general use!
Line 418... Line 434...
    lb      $v0,0($a0)
    lb      $v0,0($a0)
    beqz    $v0,puts_end
    beqz    $v0,puts_end
    addiu   $a0,1
    addiu   $a0,1
puts_wait_tx_rdy:
puts_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    andi    $v1,$v1,UART_TX_RDY
    beqz    $v1,puts_wait_tx_rdy
    beqz    $v1,puts_wait_tx_rdy
    nop
    nop
    sw      $v0,UART_TX($a2)
    sw      $v0,UART_TX($a2)
    b       puts_loop
    b       puts_loop
    nop
    nop
Line 444... Line 460...
    andi    $v0,$v0,0x0f
    andi    $v0,$v0,0x0f
    addu    $s2,$a3,$v0
    addu    $s2,$a3,$v0
    lb      $v0,0($s2)
    lb      $v0,0($s2)
put_hex_wait_tx_rdy:
put_hex_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    andi    $v1,$v1,UART_TX_RDY
    beqz    $v1,put_hex_wait_tx_rdy
    beqz    $v1,put_hex_wait_tx_rdy
    nop
    nop
    sw      $v0,UART_TX($a2)
    sw      $v0,UART_TX($a2)
 
 
    bnez    $a1,put_hex_loop
    bnez    $a1,put_hex_loop

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