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signal cpu_code_rd : t_word;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr : t_word;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_cache_enable : std_logic;
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-- interface to i/o
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-- interface to i/o
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable=> cpu_cache_enable,
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ic_invalidate=>cpu_ic_invalidate,
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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);
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);
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => '1',
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cache_enable => cpu_cache_enable,
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ic_invalidate => cpu_ic_invalidate,
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data => mpu_io_rd_data,
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io_rd_data => mpu_io_rd_data,
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io_wr_data => mpu_io_wr_data,
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io_wr_data => mpu_io_wr_data,
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io_rd_addr => mpu_io_rd_addr,
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io_rd_addr => mpu_io_rd_addr,
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