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[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Diff between revs 102 and 113

Rev 102	Rev 113
Line 15...	Line 15...
`use ieee.std_logic_unsigned.all;`	`use ieee.std_logic_unsigned.all;`
`use work.mips_pkg.all;`	`use work.mips_pkg.all;`

`entity mips_mpu is`	`entity mips_mpu is`
`generic (`	`generic (`
	`CLOCK_FREQ : integer := 50000000;`
`SRAM_ADDR_SIZE : integer := 17`	`SRAM_ADDR_SIZE : integer := 17`
`);`	`);`
`port(`	`port(`
`clk : in std_logic;`	`clk : in std_logic;`
`reset : in std_logic;`	`reset : in std_logic;`
Line 201...	Line 202...


`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`

`serial_rx : entity work.rs232_rx`	`serial_rx : entity work.rs232_rx`
	`generic map (`
	`CLOCK_FREQ => CLOCK_FREQ`
	`)`
`port map(`	`port map(`
`rxd => uart_rxd,`	`rxd => uart_rxd,`
`data_rx => uart_data_rx,`	`data_rx => uart_data_rx,`
`rx_rdy => uart_rx_rdy,`	`rx_rdy => uart_rx_rdy,`
`read_rx => uart_read_rx,`	`read_rx => uart_read_rx,`
Line 233...	Line 237...
`mpu_io_wr_addr(31 downto 28)=X"2" and`	`mpu_io_wr_addr(31 downto 28)=X"2" and`
`mpu_io_wr_addr(15 downto 12)=X"0"`	`mpu_io_wr_addr(15 downto 12)=X"0"`
`else '0';`	`else '0';`

`serial_tx : entity work.rs232_tx`	`serial_tx : entity work.rs232_tx`
	`generic map (`
	`CLOCK_FREQ => CLOCK_FREQ`
	`)`
`port map(`	`port map(`
`clk => clk,`	`clk => clk,`
`reset => reset,`	`reset => reset,`
`rdy => uart_tx_rdy,`	`rdy => uart_tx_rdy,`
`load => uart_write,`	`load => uart_write,`