| Line 40... |
Line 40... |
sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_oe_n : out std_logic;
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sram_oe_n : out std_logic;
|
|
|
-- UART
|
-- UART
|
uart_rxd : in std_logic;
|
uart_rxd : in std_logic;
|
uart_txd : out std_logic
|
uart_txd : out std_logic;
|
|
|
|
-- Debug info
|
|
debug_info : out t_debug_info
|
);
|
);
|
end; --entity mips_mpu
|
end; --entity mips_mpu
|
|
|
architecture rtl of mips_mpu is
|
architecture rtl of mips_mpu is
|
|
|
| Line 58... |
Line 61... |
signal cpu_data_wr : t_word;
|
signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_cache_enable : std_logic;
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signal cpu_cache_enable : std_logic;
|
|
signal unmapped_access : std_logic;
|
|
|
|
|
-- interface to i/o
|
-- interface to i/o
|
signal mpu_io_rd_data : std_logic_vector(31 downto 0);
|
signal mpu_io_rd_data : std_logic_vector(31 downto 0);
|
signal mpu_io_wr_data : std_logic_vector(31 downto 0);
|
signal mpu_io_wr_data : std_logic_vector(31 downto 0);
|
| Line 152... |
Line 156... |
data_wr => cpu_data_wr,
|
data_wr => cpu_data_wr,
|
|
|
mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => cpu_cache_enable,
|
cache_enable => cpu_cache_enable,
|
ic_invalidate => cpu_ic_invalidate,
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ic_invalidate => cpu_ic_invalidate,
|
|
unmapped => unmapped_access,
|
|
|
-- interface to FPGA i/o devices
|
-- interface to FPGA i/o devices
|
io_rd_data => mpu_io_rd_data,
|
io_rd_data => mpu_io_rd_data,
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io_wr_data => mpu_io_wr_data,
|
io_wr_data => mpu_io_wr_data,
|
io_rd_addr => mpu_io_rd_addr,
|
io_rd_addr => mpu_io_rd_addr,
|
| Line 197... |
Line 202... |
end if;
|
end if;
|
end process fpga_ram_block;
|
end process fpga_ram_block;
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
-- Debug stuff
|
|
|
|
-- Register some debug signals. These are meant to be connected to LEDs on a
|
|
-- dev board, or maybe to logic analyzer probes. They are not useful once
|
|
-- the core is fully debugged.
|
|
debug_info_register:
|
|
process(clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
if reset='1' then
|
|
debug_info.unmapped_access <= '0';
|
|
else
|
|
if unmapped_access='1' then
|
|
-- This flag will be asserted permanently after any kind of
|
|
-- unmapped access (code, data read or data write).
|
|
debug_info.unmapped_access <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
debug_info.cache_enabled <= cpu_cache_enable;
|
|
end if;
|
|
end process debug_info_register;
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
serial_rx : entity work.rs232_rx
|
serial_rx : entity work.rs232_rx
|
