| Line 80... |
Line 80... |
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-- Block ram
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-- Block ram
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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type t_bram is array(0 to (BRAM_SIZE)-1) of t_word;
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-- bram0 is LSB, bram3 is MSB
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-- bram0 is LSB, bram3 is MSB
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signal bram3 : t_bram := (@code3@);
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--signal bram3 : t_bram := (@ code3@);
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signal bram2 : t_bram := (@code2@);
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--signal bram2 : t_bram := (@ code2@);
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signal bram1 : t_bram := (@code1@);
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--signal bram1 : t_bram := (@ code1@);
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signal bram0 : t_bram := (@code0@);
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--signal bram0 : t_bram := (@ code0@);
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signal bram : t_bram := (@code-32bit@);
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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signal bram_rd_addr : t_bram_address;
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signal bram_rd_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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Line 181... |
fpga_ram_block:
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fpga_ram_block:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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bram_rd_data <=
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--bram_rd_data <=
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bram3(conv_integer(unsigned(bram_rd_addr))) &
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-- bram3(conv_integer(unsigned(bram_rd_addr))) &
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bram2(conv_integer(unsigned(bram_rd_addr))) &
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-- bram2(conv_integer(unsigned(bram_rd_addr))) &
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bram1(conv_integer(unsigned(bram_rd_addr))) &
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-- bram1(conv_integer(unsigned(bram_rd_addr))) &
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bram0(conv_integer(unsigned(bram_rd_addr)));
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-- bram0(conv_integer(unsigned(bram_rd_addr)));
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bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
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end if;
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end if;
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end process fpga_ram_block;
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end process fpga_ram_block;
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-- FIXME this should be in parent block
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-- FIXME this should be in parent block
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