| Line 44... |
Line 44... |
);
|
);
|
end; --entity mips_mpu
|
end; --entity mips_mpu
|
|
|
architecture rtl of mips_mpu is
|
architecture rtl of mips_mpu is
|
|
|
|
|
signal reset_sync : std_logic_vector(2 downto 0);
|
|
|
|
-- interface cpu-cache
|
-- interface cpu-cache
|
signal cpu_data_rd_addr : t_word;
|
signal cpu_data_rd_addr : t_word;
|
signal cpu_data_rd_vma : std_logic;
|
signal cpu_data_rd_vma : std_logic;
|
signal cpu_data_rd : t_word;
|
signal cpu_data_rd : t_word;
|
signal cpu_code_rd_addr : t_pc;
|
signal cpu_code_rd_addr : t_pc;
|
| Line 191... |
Line 188... |
bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
|
bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
|
|
|
end if;
|
end if;
|
end process fpga_ram_block;
|
end process fpga_ram_block;
|
|
|
-- FIXME this should be in parent block
|
|
reset_synchronization:
|
|
process(clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
reset_sync(2) <= reset;
|
|
reset_sync(1) <= reset_sync(2);
|
|
reset_sync(0) <= reset_sync(1);
|
|
end if;
|
|
end process reset_synchronization;
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
| Line 214... |
Line 201... |
rxd => uart_rxd,
|
rxd => uart_rxd,
|
data_rx => OPEN, --rs232_data_rx,
|
data_rx => OPEN, --rs232_data_rx,
|
rx_rdy => uart_rx_rdy,
|
rx_rdy => uart_rx_rdy,
|
read_rx => '1', --read_rx,
|
read_rx => '1', --read_rx,
|
clk => clk,
|
clk => clk,
|
reset => reset_sync(0)
|
reset => reset
|
);
|
);
|
|
|
|
|
uart_write_tx <= '1'
|
uart_write_tx <= '1'
|
when mpu_io_byte_we/="0000" and mpu_io_wr_addr(31 downto 28)=X"2"
|
when mpu_io_byte_we/="0000" and mpu_io_wr_addr(31 downto 28)=X"2"
|
else '0';
|
else '0';
|
|
|
serial_tx : entity work.rs232_tx
|
serial_tx : entity work.rs232_tx
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset_sync(0),
|
reset => reset,
|
rdy => uart_tx_rdy,
|
rdy => uart_tx_rdy,
|
load => uart_write_tx,
|
load => uart_write_tx,
|
data_i => mpu_io_wr_data(7 downto 0),
|
data_i => mpu_io_wr_data(7 downto 0),
|
txd => uart_txd
|
txd => uart_txd
|
);
|
);
|
