URL https://opencores.org/ocsvn/ion/ion/trunk

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[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Diff between revs 59 and 65

Rev 59	Rev 65
Line 206...	Line 206...
`reset => reset`	`reset => reset`
`);`	`);`


`uart_write_tx <= '1'`	`uart_write_tx <= '1'`
`when mpu_io_byte_we/="0000" and mpu_io_wr_addr(31 downto 28)=X"2"`	`when mpu_io_byte_we/="0000" and`
	`mpu_io_wr_addr(31 downto 28)=X"2" and`
	`mpu_io_wr_addr(15 downto 12)=X"0"`
`else '0';`	`else '0';`

`serial_tx : entity work.rs232_tx`	`serial_tx : entity work.rs232_tx`
`port map(`	`port map(`
`clk => clk,`	`clk => clk,`
Line 223...	Line 225...

`-- UART read registers; only status, and hardwired, for the time being`	`-- UART read registers; only status, and hardwired, for the time being`
`data_uart <= data_uart_status; -- FIXME no data rx yet`	`data_uart <= data_uart_status; -- FIXME no data rx yet`
`data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;`	`data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;`

`mpu_io_rd_data <= data_uart;`	`mpu_io_rd_data <=`
	`data_uart when mpu_io_rd_addr(15 downto 12)=X"0" else`
	`io_rd_data;`

`-- io_rd_data`	`-- io_rd_data`
`io_rd_addr <= mpu_io_rd_addr;`	`io_rd_addr <= mpu_io_rd_addr;`
`io_wr_addr <= mpu_io_wr_addr;`	`io_wr_addr <= mpu_io_wr_addr;`
`io_wr_data <= mpu_io_wr_data;`	`io_wr_data <= mpu_io_wr_data;`