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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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-- interface to UARTs
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-- interface to UARTs
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signal data_uart : t_word;
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signal uart_rd_word : t_word;
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signal data_uart_status : t_word;
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signal uart_tx_rdy : std_logic := '1';
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_write_tx : std_logic;
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signal uart_write : std_logic;
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signal uart_read : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_data_rx : std_logic_vector(7 downto 0);
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-- Block ram
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-- Block ram
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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serial_rx : entity work.rs232_rx
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serial_rx : entity work.rs232_rx
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port map(
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port map(
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rxd => uart_rxd,
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rxd => uart_rxd,
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data_rx => OPEN, --rs232_data_rx,
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data_rx => uart_data_rx,
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rx_rdy => uart_rx_rdy,
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rx_rdy => uart_rx_rdy,
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read_rx => '1', --read_rx,
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read_rx => uart_read_rx,
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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);
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);
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uart_write_tx <= '1'
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-- '1'-> Read some UART register (0x2---0---)
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uart_read <= '1'
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when mpu_io_rd_vma='1' and
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mpu_io_rd_addr(31 downto 28)=X"2" and
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mpu_io_rd_addr(15 downto 12)=X"0"
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else '0';
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-- '1'-> Read UART Rx data (0x2---0-0-)
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-- (This signal clears the RX 1-char buffer)
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uart_read_rx <= '1'
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when uart_read='1' and
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mpu_io_rd_addr( 7 downto 4)=X"0"
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else '0';
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-- '1'-> Write UART Tx register (trigger UART Tx) (0x20000000)
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uart_write <= '1'
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when mpu_io_byte_we/="0000" and
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when mpu_io_byte_we/="0000" and
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mpu_io_wr_addr(31 downto 28)=X"2" and
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mpu_io_wr_addr(31 downto 28)=X"2" and
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mpu_io_wr_addr(15 downto 12)=X"0"
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mpu_io_wr_addr(15 downto 12)=X"0"
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else '0';
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else '0';
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serial_tx : entity work.rs232_tx
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serial_tx : entity work.rs232_tx
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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rdy => uart_tx_rdy,
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rdy => uart_tx_rdy,
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load => uart_write_tx,
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load => uart_write,
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data_i => mpu_io_wr_data(7 downto 0),
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data_i => mpu_io_wr_data(7 downto 0),
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txd => uart_txd
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txd => uart_txd
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);
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);
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-- UART read registers; only status, and hardwired, for the time being
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-- Both UART rd addresses 000 and 020 read the same word (save a mux), but only
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data_uart <= data_uart_status; -- FIXME no data rx yet
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-- address 000 clears the rx buffer.
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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uart_rd_word <= uart_data_rx & X"00000" & "00" & uart_tx_rdy & uart_rx_rdy;
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-- IO Rd mux: either the UART data/status word od the IO coming from outside
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mpu_io_rd_data <=
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mpu_io_rd_data <=
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data_uart when mpu_io_rd_addr(15 downto 12)=X"0" else
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uart_rd_word when mpu_io_rd_addr(15 downto 12)=X"0" else
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io_rd_data;
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io_rd_data;
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-- io_rd_data
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-- io_rd_data
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io_rd_addr <= mpu_io_rd_addr;
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io_rd_addr <= mpu_io_rd_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_addr <= mpu_io_wr_addr;
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