| Line 46... |
Line 46... |
constant T : time := 20 ns;
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constant T : time := 20 ns;
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-- Time the UART is unavailable after writing to the TX register
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-- Time the UART is unavailable after writing to the TX register
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-- WARNING: slite does not simulate this. The logs may be different when > 0.0!
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-- WARNING: slite does not simulate this. The logs may be different when > 0.0!
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constant SIMULATED_UART_TX_TIME : time := 0.0 us;
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constant SIMULATED_UART_TX_TIME : time := 0.0 us;
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|
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-- Simulation length in clock cycles
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-- Simulation length in clock cycles, should be long enough (you have to try...)
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-- 2000 is enough for 'hello' sample, 22000 enough for 10 digits of pi
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constant SIMULATION_LENGTH : integer := @sim_len@;
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constant SIMULATION_LENGTH : integer := @sim_len@;
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|
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-- Simulated external SRAM size in 32-bit words
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-- Simulated external SRAM size in 32-bit words
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constant SRAM_SIZE : integer := @xram_size@;
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constant SRAM_SIZE : integer := @xram_size@;
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-- Ext. SRAM address length (memory is 16 bits wide so it needs an extra address bit)
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-- Ext. SRAM address length (memory is 16 bits wide so it needs an extra address bit)
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| Line 136... |
Line 135... |
signal cpu_code_rd : t_word;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr : t_word;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_cache_enable : std_logic;
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|
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-- interface to i/o
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-- interface to i/o
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signal io_rd_data : std_logic_vector(31 downto 0);
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signal io_rd_data : std_logic_vector(31 downto 0);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_rd_addr : std_logic_vector(31 downto 2);
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signal io_rd_addr : std_logic_vector(31 downto 2);
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| Line 192... |
Line 193... |
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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|
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable=> cpu_cache_enable,
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ic_invalidate=>cpu_ic_invalidate,
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|
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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);
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);
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|
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cache: entity work.mips_cache_stub
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cache: entity work.mips_cache
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generic map (
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generic map (
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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SRAM_ADDR_SIZE => 32,-- we need the full address to decode sram vs flash
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SRAM_ADDR_SIZE => 32,-- we need the full address to decode sram vs flash
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LINE_SIZE => 4,
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LINE_SIZE => 4,
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CACHE_SIZE => 256
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CACHE_SIZE => 256
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| Line 222... |
Line 225... |
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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|
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => '1',
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cache_enable => cpu_cache_enable,
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ic_invalidate => cpu_ic_invalidate,
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|
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data => io_rd_data,
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io_rd_data => io_rd_data,
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io_wr_data => io_wr_data,
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io_wr_data => io_wr_data,
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io_rd_addr => io_rd_addr,
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io_rd_addr => io_rd_addr,
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