| Line 21... |
Line 21... |
-- expect it.
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-- expect it.
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--
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--
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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--##############################################################################
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--##############################################################################
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library ieee,modelsim_lib;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use std.textio.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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use work.mips_tb_pkg.all;
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use modelsim_lib.util.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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entity @entity_name@ is
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entity @entity_name@ is
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end;
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end;
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| Line 71... |
Line 68... |
signal bram_rd_addr : t_bram_address;
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signal bram_rd_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_rd_data : t_word;
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signal bram_rd_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_byte_we : std_logic_vector(3 downto 0);
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signal bram_byte_we : std_logic_vector(3 downto 0);
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signal bram_data_rd_vma : std_logic;
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-- bram0 is LSB, bram3 is MSB
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-- bram0 is LSB, bram3 is MSB
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signal bram3 : t_bram := (@code3@);
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signal bram3 : t_bram := (@code3@);
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signal bram2 : t_bram := (@code2@);
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signal bram2 : t_bram := (@code2@);
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signal bram1 : t_bram := (@code1@);
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signal bram1 : t_bram := (@code1@);
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| Line 98... |
Line 96... |
signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal done : std_logic := '0';
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signal done : std_logic := '0';
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-- interface to asynchronous 16-bit-wide external SRAM
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-- interface to asynchronous 16-bit-wide external SRAM
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signal sram_address : std_logic_vector(SRAM_ADDR_SIZE-1 downto 1);
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signal sram_address : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_databus : std_logic_vector(15 downto 0);
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signal sram_databus : std_logic_vector(15 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_oe_n : std_logic;
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signal sram_oe_n : std_logic;
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-- interface cpu-cache
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-- interface cpu-cache
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| Line 127... |
Line 125... |
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Logging signals
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-- Logging signals
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-- These are internal CPU signal mirrored using Modelsim's SignalSpy
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signal rbank : t_rbank;
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signal pc, cp0_epc : std_logic_vector(31 downto 2);
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signal reg_hi, reg_lo : t_word;
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signal negate_reg_lo : std_logic;
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signal ld_upper_byte : std_logic;
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signal ld_upper_hword : std_logic;
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signal data_rd_vma : std_logic;
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signal code_rd_vma : std_logic;
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signal data_rd_address : std_logic_vector(31 downto 0);
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-- Log file
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-- Log file
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file l_file: TEXT open write_mode is "hw_sim_log.txt";
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file log_file: TEXT open write_mode is "hw_sim_log.txt";
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-- Console output log file
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-- Console output log file
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file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
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file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
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-- Maximum line size of for console output log. Lines longer than this will be
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-- Maximum line size of for console output log. Lines longer than this will be
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| Line 153... |
Line 140... |
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-- Console log line buffer
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-- Console log line buffer
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signal con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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signal con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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signal con_line_ix : integer := 1;
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signal con_line_ix : integer := 1;
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signal log_info : t_log_info;
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-- Debug signals ---------------------------------------------------------------
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-- Debug signals ---------------------------------------------------------------
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signal full_rd_addr : std_logic_vector(31 downto 0);
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signal full_rd_addr : std_logic_vector(31 downto 0);
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signal full_wr_addr : std_logic_vector(31 downto 0);
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signal full_wr_addr : std_logic_vector(31 downto 0);
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| Line 208... |
Line 197... |
data_wr_addr => cpu_data_wr_addr,
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data_wr_addr => cpu_data_wr_addr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => '1',
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data => io_rd_data,
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io_rd_data => io_rd_data,
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io_wr_data => io_wr_data,
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io_wr_data => io_wr_data,
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io_rd_addr => io_rd_addr,
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io_rd_addr => io_rd_addr,
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| Line 223... |
Line 213... |
bram_rd_data => bram_rd_data,
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bram_rd_data => bram_rd_data,
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bram_wr_data => bram_wr_data,
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bram_wr_data => bram_wr_data,
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bram_rd_addr => bram_rd_addr,
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bram_rd_addr => bram_rd_addr,
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bram_wr_addr => bram_wr_addr,
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bram_wr_addr => bram_wr_addr,
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bram_byte_we => bram_byte_we,
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bram_byte_we => bram_byte_we,
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bram_data_rd_vma=> bram_data_rd_vma,
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-- interface to asynchronous 16-bit-wide external SRAM
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-- interface to asynchronous 16-bit-wide external SRAM
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sram_address => sram_address,
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sram_address => sram_address,
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sram_databus => sram_databus,
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sram_databus => sram_databus,
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sram_byte_we_n => sram_byte_we_n,
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sram_byte_we_n => sram_byte_we_n,
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| Line 301... |
Line 292... |
sram0(conv_integer(unsigned(sram_address))) when sram_oe_n='0'
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sram0(conv_integer(unsigned(sram_address))) when sram_oe_n='0'
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else (others => 'Z');
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else (others => 'Z');
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-- Do a very basic simulation of an external SRAM
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-- Do a very basic simulation of an external SRAM
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simulated_sram:
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simulated_sram:
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process(sram_byte_we_n, sram_address)
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process(sram_byte_we_n, sram_address, sram_oe_n)
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begin
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begin
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-- FIXME should add OE\ to control logic
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-- Write cycle
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-- FIXME should add OE\ to write control logic
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if sram_byte_we_n'event or sram_address'event then
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if sram_byte_we_n'event or sram_address'event then
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if sram_byte_we_n(1)='0' then
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if sram_byte_we_n(1)='0' then
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sram1(conv_integer(unsigned(sram_address))) <= sram_databus(15 downto 8);
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sram1(conv_integer(unsigned(sram_address))) <= sram_databus(15 downto 8);
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end if;
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end if;
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if sram_byte_we_n(0)='0' then
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if sram_byte_we_n(0)='0' then
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sram0(conv_integer(unsigned(sram_address))) <= sram_databus( 7 downto 0);
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sram0(conv_integer(unsigned(sram_address))) <= sram_databus( 7 downto 0);
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end if;
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end if;
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end if;
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end if;
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-- Read cycle
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-- FIXME should add some verification of /WE
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if sram_oe_n'event or sram_address'event then
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if sram_oe_n='0' then
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sram_databus <=
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sram1(conv_integer(unsigned(sram_address))) &
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sram0(conv_integer(unsigned(sram_address)));
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else
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sram_databus <= (others => 'Z');
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end if;
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end if;
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end process simulated_sram;
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end process simulated_sram;
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simulated_io:
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simulated_io:
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process(clk)
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process(clk)
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| Line 363... |
Line 368... |
end if;
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end if;
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end if;
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end if;
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end process simulated_io;
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end process simulated_io;
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-- UART read registers; only status, and hardwired, for the time being
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-- UART read registers; only status, and hardwired, for the time being
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io_rd_data <= X"00000003";
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data_uart <= data_uart_status;
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data_uart <= data_uart_status;
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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log_execution:
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signalspy_rbank:
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process
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process
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begin
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begin
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init_signal_spy("/@entity_name@/cpu/p1_rbank", "rbank", 0, -1);
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log_cpu_activity(clk, reset, done,
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init_signal_spy("/@entity_name@/cpu/p0_pc_reg", "pc", 0, -1);
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"@entity_name@/cpu", log_info, "log_info", log_file);
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init_signal_spy("/@entity_name@/cpu/mult_div/upper_reg", "reg_hi", 0, -1);
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init_signal_spy("/@entity_name@/cpu/mult_div/lower_reg", "reg_lo", 0, -1);
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init_signal_spy("/@entity_name@/cpu/mult_div/negate_reg", "negate_reg_lo", 0, -1);
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init_signal_spy("/@entity_name@/cpu/cp0_epc", "cp0_epc", 0, -1);
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init_signal_spy("/@entity_name@/cpu/p2_ld_upper_byte", "ld_upper_byte", 0, -1);
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init_signal_spy("/@entity_name@/cpu/p2_ld_upper_byte", "ld_upper_hword", 0, -1);
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init_signal_spy("/@entity_name@/cpu/data_rd_vma", "data_rd_vma", 0, -1);
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init_signal_spy("/@entity_name@/cpu/code_rd_vma", "code_rd_vma", 0, -1);
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wait;
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wait;
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end process signalspy_rbank;
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end process log_execution;
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log_cpu_activity:
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process(clk)
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variable prev_rbank : t_rbank := (others => X"00000000");
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variable ri : std_logic_vector(7 downto 0);
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variable full_pc : t_word := (others => '0');
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variable prev_pc : t_word := (others => '0');
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variable prev_hi : t_word := (others => '0');
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variable prev_lo : t_word := (others => '0');
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variable prev_epc : std_logic_vector(31 downto 2) := (others => '0');
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variable wr_data : t_word := (others => '0');
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variable temp : t_word := (others => '0');
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variable size : std_logic_vector(7 downto 0) := X"00";
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variable prev_vma_data : std_logic := '0';
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variable prev_rd_addr : t_word := (others => '0');
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variable prev_rd_data : t_word := (others => '0');
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variable rd_size : std_logic_vector(7 downto 0) := X"00";
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begin
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-- we'll be sampling control & data signals at falling edge, when
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-- they're stable
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if clk'event and clk='0' then
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if reset='0' then
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-- log loads (data only)
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-- IMPORTANT: memory reads should be logged first because we're
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-- logging them the cycle after they actually happen. If you put
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-- the log code after any other log, the order of the operations
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-- will appear wrong in the log even though it is not.
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if prev_vma_data='1' and cpu_mem_wait='0' then
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if ld_upper_hword='1' then
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rd_size := X"04";
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elsif ld_upper_byte='1' then
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rd_size := X"02";
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else
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rd_size := X"01";
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end if;
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print(l_file, "("& hstr(prev_pc) &") ["& hstr(prev_rd_addr) &"] <"&
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"**"&
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--hstr(rd_size)&
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">="& hstr(cpu_data_rd)& " RD");
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end if;
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prev_rd_data := cpu_data_rd;
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if cpu_mem_wait='0' then
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prev_vma_data := data_rd_vma;
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prev_rd_addr := full_rd_addr;
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end if;
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-- log register changes
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ri := X"00";
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for i in 0 to 31 loop
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if prev_rbank(i)/=rbank(i) then
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print(l_file, "("& hstr(full_pc)& ") ["& hstr(ri)& "]="& hstr(rbank(i)));
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end if;
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ri := ri + 1;
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end loop;
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-- log aux register changes, only when pipeline is not stalled
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if prev_lo /= reg_lo and reg_lo(0)/='U' and code_rd_vma='1' then
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-- we're observing the value of reg_lo, but the mult core
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-- will output the negated value in some cases. We
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-- have to mimic that behavior.
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if negate_reg_lo='1' then
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-- negate reg_lo before displaying
|
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prev_lo := not reg_lo;
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prev_lo := prev_lo + 1;
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print(l_file, "("& hstr(full_pc)& ") [LO]="& hstr(prev_lo));
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else
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print(l_file, "("& hstr(full_pc)& ") [LO]="& hstr(reg_lo));
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end if;
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end if;
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if prev_hi /= reg_hi and reg_hi(0)/='U' and code_rd_vma='1' then
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print(l_file, "("& hstr(full_pc)& ") [HI]="& hstr(reg_hi));
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end if;
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if prev_epc /= cp0_epc and cp0_epc(31)/='U' then
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temp := cp0_epc & "00";
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print(l_file, "("& hstr(full_pc)& ") [EP]="& hstr(temp));
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end if;
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-- 'remember' last value of hi and lo only when pipeline is not
|
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-- stalled; that's because we don't want to be tracking the
|
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-- changing values when mul/div is running (because the SW
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-- simulator doesn't)
|
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if code_rd_vma='1' then
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prev_hi := reg_hi;
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prev_lo := reg_lo;
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end if;
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full_pc := pc & "00";
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prev_pc := full_pc;
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prev_rbank := rbank;
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prev_epc := cp0_epc;
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-- log writes
|
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if cpu_byte_we/="0000" then
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wr_data := X"00000000";
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if cpu_byte_we(3)='1' then
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wr_data(31 downto 24) := cpu_data_wr(31 downto 24);
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end if;
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if cpu_byte_we(2)='1' then
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wr_data(23 downto 16) := cpu_data_wr(23 downto 16);
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end if;
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if cpu_byte_we(1)='1' then
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wr_data(15 downto 8) := cpu_data_wr(15 downto 8);
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end if;
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if cpu_byte_we(0)='1' then
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wr_data( 7 downto 0) := cpu_data_wr( 7 downto 0);
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end if;
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size := "0000" & cpu_byte_we; -- mask, really
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print(l_file, "("& hstr(full_pc) &") ["& hstr(full_wr_addr) &"] |"& hstr(size)& "|="& hstr(wr_data)& " WR" );
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end if;
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if full_code_addr(31 downto 28)="1111" then
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print(l_file, "ERROR: Code addressed upper memory area" );
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end if;
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end if;
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end if;
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end process log_cpu_activity;
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end architecture @arch_name@;
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end architecture @arch_name@;
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No newline at end of file
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No newline at end of file
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