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-- bytes for each word of SRAM_SIZE
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-- bytes for each word of SRAM_SIZE
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type t_sram is array(0 to SRAM_SIZE*2-1) of std_logic_vector(7 downto 0);
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type t_sram is array(0 to SRAM_SIZE*2-1) of std_logic_vector(7 downto 0);
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signal sram1 : t_sram := (@data31@);
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signal sram1 : t_sram := (@data31@);
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signal sram0 : t_sram := (@data20@);
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signal sram0 : t_sram := (@data20@);
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-- PROM table and interface signals --------------------------------------------
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- cycle time (70 or 90 ns).
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--constant PROM_SIZE : integer := @flash_table_size@;
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--constant PROM_ADDR_SIZE : integer := log2(PROM_SIZE);
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--
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--subtype t_prom_address is std_logic_vector(PROM_ADDR_SIZE-1 downto 0);
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--type t_prom is array(0 to PROM_SIZE-1) of t_hword;
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--
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--signal prom_rd_addr : t_prom_address;
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--signal prom_databus : t_hword;
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--signal prom_oe_n : std_logic;
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--
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---- bram0 is LSB, bram3 is MSB
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--signal prom : t_prom := (@flash@);
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--
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-- I/O devices -----------------------------------------------------------------
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal uart_tx_rdy : std_logic := '1';
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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end if;
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end if;
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end if;
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end if;
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-- Read cycle
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-- Read cycle
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-- FIXME should add some verification of /WE
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-- FIXME should add some verification of /WE
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if sram_oe_n'event or sram_address'event then
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--if sram_oe_n'event or sram_address'event then
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if sram_oe_n='0' then
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-- if sram_oe_n='0' then
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sram_databus <=
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-- sram_databus <=
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sram1(conv_integer(unsigned(sram_address))) &
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-- sram1(conv_integer(unsigned(sram_address))) &
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sram0(conv_integer(unsigned(sram_address)));
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-- sram0(conv_integer(unsigned(sram_address)));
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else
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-- else
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sram_databus <= (others => 'Z');
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-- sram_databus <= (others => 'Z');
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end if;
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-- end if;
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end if;
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--end if;
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end process simulated_sram;
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end process simulated_sram;
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-- Do a very basic simulation of an external PROM wired to the same bus
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-- as the sram (both are static).
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-- prom_databus <=
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-- prom(conv_integer(unsigned(sram_address))) when prom_oe_n='0'
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-- else (others => 'Z');
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simulated_io:
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simulated_io:
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process(clk)
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process(clk)
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variable i : integer;
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variable i : integer;
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variable uart_data : integer;
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variable uart_data : integer;
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