| Line 82... |
Line 82... |
-- bytes for each word of SRAM_SIZE
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-- bytes for each word of SRAM_SIZE
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type t_sram is array(0 to SRAM_SIZE*2-1) of std_logic_vector(7 downto 0);
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type t_sram is array(0 to SRAM_SIZE*2-1) of std_logic_vector(7 downto 0);
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signal sram1 : t_sram := (@data31@);
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signal sram1 : t_sram := (@data31@);
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signal sram0 : t_sram := (@data20@);
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signal sram0 : t_sram := (@data20@);
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signal sram_chip_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_output : std_logic_vector(15 downto 0);
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-- PROM table and interface signals --------------------------------------------
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-- PROM table and interface signals --------------------------------------------
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- cycle time (70 or 90 ns).
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-- cycle time (70 or 90 ns).
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--constant PROM_SIZE : integer := @flash_table_size@;
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constant PROM_SIZE : integer := @prom_size@;
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--constant PROM_ADDR_SIZE : integer := log2(PROM_SIZE);
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constant PROM_ADDR_SIZE : integer := log2(PROM_SIZE);
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--
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--subtype t_prom_address is std_logic_vector(PROM_ADDR_SIZE-1 downto 0);
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subtype t_prom_address is std_logic_vector(PROM_ADDR_SIZE-1 downto 0);
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--type t_prom is array(0 to PROM_SIZE-1) of t_hword;
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type t_prom is array(0 to PROM_SIZE-1) of t_word;
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--
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--signal prom_rd_addr : t_prom_address;
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signal prom_rd_addr : t_prom_address;
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--signal prom_databus : t_hword;
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signal prom_output : std_logic_vector(7 downto 0);
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--signal prom_oe_n : std_logic;
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signal prom_oe_n : std_logic;
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--
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---- bram0 is LSB, bram3 is MSB
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-- bram0 is LSB, bram3 is MSB
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--signal prom : t_prom := (@flash@);
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signal prom : t_prom := (@flash@);
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--
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-- I/O devices -----------------------------------------------------------------
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-- I/O devices -----------------------------------------------------------------
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart : std_logic_vector(31 downto 0);
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Line 120... |
signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal done : std_logic := '0';
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signal done : std_logic := '0';
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-- interface to asynchronous 16-bit-wide external SRAM
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-- interface to asynchronous 16-bit-wide external SRAM
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signal sram_address : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_address : std_logic_vector(31 downto 0);
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signal sram_databus : std_logic_vector(15 downto 0);
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signal sram_data_rd : std_logic_vector(15 downto 0);
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signal sram_data_wr : std_logic_vector(15 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_oe_n : std_logic;
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signal sram_oe_n : std_logic;
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-- interface cpu-cache
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-- interface cpu-cache
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signal cpu_data_rd_addr : t_word;
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signal cpu_data_rd_addr : t_word;
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Line 202... |
);
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);
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cache: entity work.mips_cache_stub
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cache: entity work.mips_cache_stub
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generic map (
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generic map (
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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SRAM_ADDR_SIZE => 32 -- we need the full address to decode sram vs flash
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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| Line 238... |
Line 242... |
bram_byte_we => bram_byte_we,
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bram_byte_we => bram_byte_we,
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bram_data_rd_vma=> bram_data_rd_vma,
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bram_data_rd_vma=> bram_data_rd_vma,
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-- interface to asynchronous 16-bit-wide external SRAM
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-- interface to asynchronous 16-bit-wide external SRAM
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sram_address => sram_address,
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sram_address => sram_address,
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sram_databus => sram_databus,
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sram_data_rd => sram_data_rd,
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sram_data_wr => sram_data_wr,
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sram_byte_we_n => sram_byte_we_n,
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sram_byte_we_n => sram_byte_we_n,
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sram_oe_n => sram_oe_n
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sram_oe_n => sram_oe_n
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);
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);
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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Line 311... |
end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process data_ram_block;
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end process data_ram_block;
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sram_databus <=
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sram_data_rd <=
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sram1(conv_integer(unsigned(sram_address))) &
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X"00" & prom_output when sram_address(31 downto 27)="10110" else
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sram0(conv_integer(unsigned(sram_address))) when sram_oe_n='0'
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sram_output;
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-- Do a very basic simulation of an external SRAM ---------------
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sram_chip_addr <= sram_address(SRAM_ADDR_SIZE downto 1);
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-- FIXME should add some verification of /WE
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sram_output <=
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sram1(conv_integer(unsigned(sram_chip_addr))) &
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sram0(conv_integer(unsigned(sram_chip_addr))) when sram_oe_n='0'
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else (others => 'Z');
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else (others => 'Z');
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-- Do a very basic simulation of an external SRAM
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simulated_sram_write:
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simulated_sram:
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process(sram_byte_we_n, sram_address, sram_oe_n)
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process(sram_byte_we_n, sram_address, sram_oe_n)
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begin
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begin
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-- Write cycle
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-- Write cycle
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-- FIXME should add OE\ to write control logic
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-- FIXME should add OE\ to write control logic
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if sram_byte_we_n'event or sram_address'event then
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if sram_byte_we_n'event or sram_address'event then
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if sram_byte_we_n(1)='0' then
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if sram_byte_we_n(1)='0' then
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sram1(conv_integer(unsigned(sram_address))) <= sram_databus(15 downto 8);
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sram1(conv_integer(unsigned(sram_chip_addr))) <= sram_data_wr(15 downto 8);
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end if;
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end if;
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if sram_byte_we_n(0)='0' then
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if sram_byte_we_n(0)='0' then
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sram0(conv_integer(unsigned(sram_address))) <= sram_databus( 7 downto 0);
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sram0(conv_integer(unsigned(sram_chip_addr))) <= sram_data_wr( 7 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process simulated_sram_write;
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-- Read cycle
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-- FIXME should add some verification of /WE
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--if sram_oe_n'event or sram_address'event then
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-- if sram_oe_n='0' then
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-- sram_databus <=
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-- sram1(conv_integer(unsigned(sram_address))) &
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-- sram0(conv_integer(unsigned(sram_address)));
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-- else
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-- sram_databus <= (others => 'Z');
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-- end if;
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--end if;
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end process simulated_sram;
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-- Do a very basic simulation of an external PROM wired to the same bus
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-- Do a very basic simulation of an external PROM wired to the same bus
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-- as the sram (both are static).
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-- as the sram (both are static).
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-- prom_databus <=
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-- prom(conv_integer(unsigned(sram_address))) when prom_oe_n='0'
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prom_rd_addr <= sram_address(PROM_ADDR_SIZE+1 downto 2);
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-- else (others => 'Z');
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prom_oe_n <= sram_oe_n;
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prom_output <=
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prom(conv_integer(unsigned(prom_rd_addr)))(31 downto 24) when prom_oe_n='0' and sram_address(1 downto 0)="00" else
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prom(conv_integer(unsigned(prom_rd_addr)))(23 downto 16) when prom_oe_n='0' and sram_address(1 downto 0)="01" else
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prom(conv_integer(unsigned(prom_rd_addr)))(15 downto 8) when prom_oe_n='0' and sram_address(1 downto 0)="10" else
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prom(conv_integer(unsigned(prom_rd_addr)))( 7 downto 0) when prom_oe_n='0' and sram_address(1 downto 0)="11" else
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(others => 'Z');
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simulated_io:
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simulated_io:
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process(clk)
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process(clk)
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variable i : integer;
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variable i : integer;
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