| Line 127... |
Line 127... |
signal sram_data_wr : std_logic_vector(15 downto 0);
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signal sram_data_wr : std_logic_vector(15 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_byte_we_n : std_logic_vector(1 downto 0);
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signal sram_oe_n : std_logic;
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signal sram_oe_n : std_logic;
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-- interface cpu-cache
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-- interface cpu-cache
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signal cpu_data_rd_addr : t_word;
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signal cpu_data_addr : t_word;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd : t_word;
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signal cpu_data_rd : t_word;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr_addr : t_pc;
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signal cpu_data_wr : t_word;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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-- interface to i/o
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-- interface to i/o
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| Line 181... |
Line 180... |
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cpu: entity work.mips_cpu
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cpu: entity work.mips_cpu
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port map (
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port map (
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interrupt => '0',
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interrupt => '0',
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data_rd_addr=> cpu_data_rd_addr,
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data_addr => cpu_data_addr,
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data_rd_vma => cpu_data_rd_vma,
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data_rd_vma => cpu_data_rd_vma,
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data_rd => cpu_data_rd,
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data_rd => cpu_data_rd,
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code_rd_addr=> cpu_code_rd_addr,
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code_rd_addr=> cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
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data_wr_addr=> cpu_data_wr_addr,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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);
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);
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cache: entity work.mips_cache_stub
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cache: entity work.mips_cache_stub
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generic map (
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generic map (
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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SRAM_ADDR_SIZE => 32 -- we need the full address to decode sram vs flash
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SRAM_ADDR_SIZE => 32,-- we need the full address to decode sram vs flash
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LINE_SIZE => 4,
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CACHE_SIZE => 256
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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-- Interface to CPU core
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-- Interface to CPU core
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data_rd_addr => cpu_data_rd_addr,
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data_addr => cpu_data_addr,
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data_rd => cpu_data_rd,
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data_rd => cpu_data_rd,
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data_rd_vma => cpu_data_rd_vma,
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data_rd_vma => cpu_data_rd_vma,
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code_rd_addr => cpu_code_rd_addr,
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code_rd_addr => cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
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data_wr_addr => cpu_data_wr_addr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => '1',
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cache_enable => '1',
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| Line 280... |
Line 280... |
done <= '1';
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done <= '1';
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wait;
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wait;
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end process drive_uut;
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end process drive_uut;
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full_rd_addr <= cpu_data_rd_addr;
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full_rd_addr <= cpu_data_addr;
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full_wr_addr <= cpu_data_wr_addr & "00";
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full_wr_addr <= cpu_data_addr(31 downto 2) & "00";
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full_code_addr <= cpu_code_rd_addr & "00";
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full_code_addr <= cpu_code_rd_addr & "00";
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data_ram_block:
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data_ram_block:
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process(clk)
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process(clk)
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begin
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begin
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