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# Get common makefile stuff (toolchain & system config)
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# Get common makefile stuff (toolchain & system config)
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include ../common/makefile
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include ../common/makefile
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# We'll run the simulation for 2000 clock cycles
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# We'll run the simulation for 2000 clock cycles
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SIM_LENGTH = 2000
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SIM_LENGTH = 3000
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clean:
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clean:
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-$(RM) -f *.o *.obj *.map *.lst *.hex \
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-$(RM) -f *.o *.obj *.map *.lst *.hex \
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*.exe *.axf *.code *.data *.bin
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*.exe *.axf *.code *.data *.bin
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opcodes:
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opcodes:
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$(AS_MIPS) -o opcodes.o opcodes.s
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$(AS_MIPS) -o opcodes.o opcodes.s
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$(LD_MIPS) -Ttext 0 -eentry -Map opcodes.map -s -N -o opcodes.axf opcodes.o
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$(LD_MIPS) -Ttext 0 -eentry -Map opcodes.map -s -N -o opcodes.axf opcodes.o
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-@$(DUMP_MIPS) -I elf32-big --disassemble opcodes.axf > opcodes.lst
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-@$(DUMP_MIPS) -I elf32-big --disassemble opcodes.axf > opcodes.lst
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@# Dump only text segment, no .rodata on this program
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# Dump only text segment, no .rodata on this program
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$(COPY_MIPS) -I elf32-big -j .text -O binary opcodes.axf opcodes.bin
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$(COPY_MIPS) -I elf32-big -j .text -O binary opcodes.axf opcodes.bin
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# Dump data segment to file; will be empty but the TB2 template needs it
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$(COPY_MIPS) -I elf32-big -j .data -O binary opcodes.axf opcodes.data
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# Create VHDL file for simulation test bench
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# Create VHDL file for simulation test bench from TB1 template
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opcodes_sim: opcodes
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opcodes_sim: opcodes
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$(TO_VHDL) $(VHDL_FLAGS) --code opcodes.bin \
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$(TO_VHDL) --code opcodes.bin \
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--code_size $(CODE_BRAM_SIZE) --data_size $(DATA_BRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb0_template.vhdl \
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-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb0_template.vhdl \
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-o $(TB_DIR)\\mips_tb1.vhdl -e mips_tb1
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-o $(TB_DIR)\\mips_tb1.vhdl -e mips_tb1
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# Create VHDL file for simulation test bench from TB2 template
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opcodes_sim2: opcodes
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$(TO_VHDL) --code opcodes.bin --data opcodes.data\
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--code_size $(CODE_BRAM_SIZE) --data_size $(DATA_BRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
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-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2
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