| Line 20... |
Line 20... |
# conditions. Instead, it performs the operations to be tested and relies on you
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# conditions. Instead, it performs the operations to be tested and relies on you
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# to compare the logs from the logic simulation and the software simulation.
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# to compare the logs from the logic simulation and the software simulation.
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# Test that work this way have been commented with this tag: "@log"
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# Test that work this way have been commented with this tag: "@log"
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# NOTE: NOPs have been inserted after load instructions.
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# @note1: Hardware interrupt simulation
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#
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#
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# Hardware interrupts can be triggered by writing to a bank of debug
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# registers; you can trigger any or all of the 6 hardware interrupts of the
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# R3000 architecture (i.e. excluding the 2 SW interrupts), with any delay you
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# want, measured in instruction cycles, NOT clock cycles. You can make two or
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# more IRQs assert at the same time for test purposes.
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# Both the software simulator and the VHDL simulation test bench implement
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# these debug registers.
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# Note again that the delay is given in instruction cycles.
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################################################################################
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################################################################################
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#-- Set flags below to >0 to enable/disable test assembly ------------------
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#-- Set flags below to >0 to enable/disable test assembly ------------------
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.set TEST_UNALIGNED_LOADS, 0 # unaligned loads
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.set TEST_UNALIGNED_LOADS, 0 # unaligned loads
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.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_BREAK, 1 # BREAK instruction
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.set TEST_BREAK, 1 # BREAK instruction
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# WARNING: the assembler expands div instructions, see 'as' manual
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# WARNING: the assembler expands div instructions, see 'as' manual
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.set TEST_DIV, 1 # DIV* instructions
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.set TEST_DIV, 1 # DIV* instructions
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.set TEST_MUL, 1 # MUL* instructions
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.set TEST_MUL, 1 # MUL* instructions
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.set TEST_BAD_OPCODES, 1 # Test opcode emulation trap
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.set TEST_TRAP_DELAY_EMU, 0 # Test emu of bad opcodes in delay slots
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.set TEST_HW_INTS, 1 # Test HW interrupts (@note1)
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.set USE_CACHE, 1 # Initialize and enable cache
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.set USE_CACHE, 1 # Initialize and enable cache
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.set EMU_MIPS32, 1 # Emulates selected MIPS32 opcodes
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.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache
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.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache
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.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache
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.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache
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.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words
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.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words
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| Line 81... |
Line 92... |
bne $k0,$k1,trap_invalid
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bne $k0,$k1,trap_invalid
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nop
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nop
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# Unimplemented instruction
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# Unimplemented instruction
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trap_unimplemented:
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trap_unimplemented:
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.ifgt EMU_MIPS32
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.ifgt TEST_BAD_OPCODES
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# jump to mips32 opcode emulator with c0_cause in $k0
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# jump to mips32 opcode emulator with c0_cause in $k0
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j opcode_emu
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j opcode_emu
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nop
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nop
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.else
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.else
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# just do some simple arith so the opcode tester knows we were here
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# just do some simple arith so the opcode tester knows we were here
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| Line 1239... |
Line 1250... |
sb $21,0($20)
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sb $21,0($20)
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######################################
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######################################
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#Emulated MIPS32r2 Instructions
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#Emulated MIPS32r2 Instructions
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######################################
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######################################
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.ifgt EMU_MIPS32
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.ifgt TEST_BAD_OPCODES
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ori $2,$0,'M'
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ori $2,$0,'M'
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sb $2,0($20)
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sb $2,0($20)
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ori $2,$0,'i'
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ori $2,$0,'i'
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sb $2,0($20)
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sb $2,0($20)
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ori $2,$0,'p'
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ori $2,$0,'p'
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| Line 1368... |
Line 1379... |
addiu $a1,$k0,'D'-0
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addiu $a1,$k0,'D'-0
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sb $a1,0($20)
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sb $a1,0($20)
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sb $23,0($20)
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sb $23,0($20)
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sb $21,0($20)
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sb $21,0($20)
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# FIXME should test the bad opcode emulation in delay slots
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.endif
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.endif
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# Print 'Done'; the rest of the tests are for log matching only
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# Print 'Done'; the rest of the tests are for log matching only
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ori $2,$0,'D'
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ori $2,$0,'D'
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sb $2,0($20)
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sb $2,0($20)
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ori $2,$0,'o'
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ori $2,$0,'o'
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sb $2,0($20)
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sb $2,0($20)
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| Line 1562... |
Line 1577... |
bltz $s4,test_b11
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bltz $s4,test_b11
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nop
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nop
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ori $v0,0x5503
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ori $v0,0x5503
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test_b11:
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test_b11:
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#-- Hardware interrupts -----------------------------------------
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test_hw_irq:
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.ifgt TEST_HW_INTS
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li $a0,0x20010000 # base address of debug reg block
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# Trigger IRQ_0 in 10 instruction cycles (@note1)
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#lhu $a1,10 # load irq count down register...
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li $a1,10
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sw $a1,0($a0)
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lhu $a2,20
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test_hw_irq_0:
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bnez $a2,test_hw_irq_0 # ...and wait for irq to trigger
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addiu $a2,$a2,-1
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# When we arrive here, we should have executed the irq handler if
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# the irq worked properly, so check it.
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# FIXME incomplete code, stopped work here
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.endif
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$DONE:
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$DONE:
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j $DONE
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j $DONE # End in an infinite loop
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nop
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nop
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# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
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# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
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setup_cache:
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setup_cache:
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li $a0,0x00010002 # Enable I-cache line invalidation
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li $a0,0x00010002 # Enable I-cache line invalidation
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