| Line 7... |
Line 7... |
# project (http://opencores.org/project,plasma).
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# project (http://opencores.org/project,plasma).
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# COPYRIGHT: Software placed into the public domain by the original author.
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# COPYRIGHT: Software placed into the public domain by the original author.
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# Software 'as is' without warranty. Author liable for nothing.
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# Software 'as is' without warranty. Author liable for nothing.
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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#
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# This assembly file tests all of the opcodes supported by the Ion core.
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# This assembly file tests all of the opcodes supported by the Ion core.
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# This test assumes that address 0x20000000 is the UART write register.
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# This test assumes that address 0x20000000 is the UART write register.
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# Successful tests will print out "A" or "AB" or "ABC" or ....
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# Successful tests will print out "A" or "AB" or "ABC" or ....
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# Missing letters or letters out of order indicate a failure.
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# Missing letters or letters out of order indicate a failure.
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# NOTE: This test bench relies on the simulation logs to catch errors. That is,
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# NOTE: This test bench relies on the simulation logs to catch errors. That is,
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# unlike the original Plasma code, this one does not test the test success
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# unlike the original Plasma code, this one does not test the test success
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# conditions. instead, it performs the operations to be tested and relies on you
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# conditions. instead, it performs the operations to be tested and relies on you
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# to compare the logs from the logic simulation and the software simulation.
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# to compare the logs from the logic simulation and the software simulation.
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| Line 30... |
Line 30... |
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.set TEST_UNALIGNED_LOADS, 0 # unaligned loads
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.set TEST_UNALIGNED_LOADS, 0 # unaligned loads
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.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_BREAK, 1 # BREAK instruction
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.set TEST_BREAK, 1 # BREAK instruction
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# WARNING: the assembler expands div instructions, see 'as' manual
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# WARNING: the assembler expands div instructions, see 'as' manual
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.set TEST_DIV, 0 # DIV* instructions
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.set TEST_DIV, 1 # DIV* instructions
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.set TEST_MUL, 0 # MUL* instructions
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.set TEST_MUL, 1 # MUL* instructions
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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.text
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.text
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.align 2
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.align 2
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| Line 731... |
Line 731... |
sb $23,0($20)
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sb $23,0($20)
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sb $21,0($20)
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sb $21,0($20)
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.endif
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.endif
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#q: SYSCALL
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#q: SYSCALL
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ori $2,$0,'q'
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ori $2,$0,'q' # check if it jumpts to trap vector and comes back
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sb $2,0($20)
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sb $2,0($20)
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ori $4,$0,61
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ori $4,$0,61
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syscall 0
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syscall 0
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addi $4,$4,-1
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addi $4,$4,-1
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sb $4,0($20)
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sb $4,0($20)
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syscall 0 # check if load instruction is aborted (@log)
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lb $2,16($2)
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syscall 0 # check if jump instruction is aborted (@log)
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j syscall_jump_test1
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add $4,$4,5
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syscall_jump_test1:
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add $4,$4,1 # make sure the jump shows in the log (@log)
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# TODO traps in delay slots not supported yet
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#j syscall_jump_test2 # check if syscall works in delay slot of jump
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#break 0
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nop
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j syscall_continue
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nop
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syscall_jump_test2:
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add $4,$4,1
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syscall_continue:
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sb $23,0($20)
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sb $23,0($20)
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sb $21,0($20)
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sb $21,0($20)
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######################################
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######################################
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