| Line 32... |
Line 32... |
.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_UNALIGNED_STORES, 0 # unaligned stores
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.set TEST_BREAK, 1 # BREAK instruction
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.set TEST_BREAK, 1 # BREAK instruction
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# WARNING: the assembler expands div instructions, see 'as' manual
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# WARNING: the assembler expands div instructions, see 'as' manual
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.set TEST_DIV, 1 # DIV* instructions
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.set TEST_DIV, 1 # DIV* instructions
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.set TEST_MUL, 1 # MUL* instructions
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.set TEST_MUL, 1 # MUL* instructions
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.set USE_CACHE, 1 # Initialize and enable cache
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.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache
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.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache
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.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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.text
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.text
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.align 2
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.align 2
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| Line 107... |
Line 112... |
addi $k1,$k1,4 # skip jump instruction too
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addi $k1,$k1,4 # skip jump instruction too
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jr $k1 # (we just added 8 to epc)
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jr $k1 # (we just added 8 to epc)
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StartTest:
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StartTest:
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.ifgt USE_CACHE
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jal setup_cache
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nop
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.else
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mtc0 $0,$12 # disable interrupts, disable cache
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mtc0 $0,$12 # disable interrupts, disable cache
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.endif
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lui $20,0x2000 # serial port write address
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lui $20,0x2000 # serial port write address
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ori $21,$0,'\n' # <CR> character
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ori $21,$0,'\n' # <CR> character
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ori $22,$0,'X' # 'X' letter
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ori $22,$0,'X' # 'X' letter
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ori $23,$0,'\r'
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ori $23,$0,'\r'
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ori $24,$0,0x0f80 # temp memory
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ori $24,$0,0x0f80 # temp memory
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| Line 1391... |
Line 1401... |
bltz $s4,test_b11
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bltz $s4,test_b11
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nop
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nop
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ori $v0,0x5503
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ori $v0,0x5503
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test_b11:
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test_b11:
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$DONE:
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$DONE:
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j $DONE
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j $DONE
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nop
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nop
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.set reorder
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# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
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.end entry
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setup_cache:
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lui $a0,0x0001 # Enable I-cache line invalidation
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mtc0 $a0,$12
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# In order to invalidate a I-Cache line we have to write its tag number to
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# any address while bits CP0[12].17:16=01. The write will be executed as a
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# regular write too, as a side effect, so we need to choose a harmless
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# target address. The BSS will do -- it will be cleared later.
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# We'll cover all ICACHE_NUM_LINES lines no matter what the starting
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# address is, anyway.
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la $a0,__bss_start
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li $a2,0
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li $a1,ICACHE_NUM_LINES-1
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inv_i_cache_loop:
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sw $a2,0($a0)
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blt $a2,$a1,inv_i_cache_loop
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addi $a2,1
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# Now, the D-Cache is different. To invalidate a D-Cache line you just
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# read from it (by proper selection of a dummy target address) while bits
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# CP0[12].17:16=01. The data read is undefined and should be discarded.
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li $a0,0 # Use any base address that is mapped
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li $a2,0
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li $a1,DCACHE_NUM_LINES-1
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inv_d_cache_loop:
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lw $zero,0($a0)
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addi $a0,DCACHE_LINE_SIZE*4
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blt $a2,$a1,inv_d_cache_loop
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addi $a2,1
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lui $a1,0x0002 # Leave with cache enabled
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jr $ra
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mtc0 $a1,$12
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.set reorder
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.end entry
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