| Line 68... |
Line 68... |
# Besides, we have to look out for the branch delay flag (BD)
|
# Besides, we have to look out for the branch delay flag (BD)
|
# We'll just increment $4 by a fixed constant depending on the cause
|
# We'll just increment $4 by a fixed constant depending on the cause
|
# so we will not save any registers (there's no stack anyway)
|
# so we will not save any registers (there's no stack anyway)
|
InterruptVector:
|
InterruptVector:
|
mfc0 $k0,$13 # Get trap cause code
|
mfc0 $k0,$13 # Get trap cause code
|
|
srl $k0,$k0,2
|
andi $k0,$k0,0x01f
|
andi $k0,$k0,0x01f
|
ori $k1,$zero,0x8 # was it a syscall?
|
ori $k1,$zero,0x8 # was it a syscall?
|
beq $k0,$k1,trap_syscall
|
beq $k0,$k1,trap_syscall
|
addi $k1,$k1,0x1 # was it a break?
|
addi $k1,$k1,0x1 # was it a break?
|
beq $k0,$k1,trap_break
|
beq $k0,$k1,trap_break
|
| Line 119... |
Line 120... |
jal setup_cache
|
jal setup_cache
|
nop
|
nop
|
.else
|
.else
|
mtc0 $0,$12 # disable interrupts, disable cache
|
mtc0 $0,$12 # disable interrupts, disable cache
|
.endif
|
.endif
|
|
|
|
li $k0,0x00020000 # enter user mode
|
|
mtc0 $k0,$12
|
|
ori $k0,0x01
|
|
mtc0 $k0,$12 # verify COP* in user mode triggers trap (@log)
|
|
|
lui $20,0x2000 # serial port write address
|
lui $20,0x2000 # serial port write address
|
ori $21,$0,'\n' # <CR> character
|
ori $21,$0,'\n' # <CR> character
|
ori $22,$0,'X' # 'X' letter
|
ori $22,$0,'X' # 'X' letter
|
ori $23,$0,'\r'
|
ori $23,$0,'\r'
|
ori $24,$0,0x0f80 # temp memory
|
ori $24,$0,0x0f80 # temp memory
|
|
|
sb $23,0($20)
|
sb $23,0($20) # test a bunch of byte-wide stores
|
sb $21,0($20)
|
sb $21,0($20)
|
sb $23,0($20)
|
sb $23,0($20)
|
sb $21,0($20)
|
sb $21,0($20)
|
sb $23,0($20)
|
sb $23,0($20)
|
sb $21,0($20)
|
sb $21,0($20)
|
| Line 785... |
Line 792... |
add $4,$4,5
|
add $4,$4,5
|
|
|
syscall_jump_test1:
|
syscall_jump_test1:
|
add $4,$4,1 # make sure the jump shows in the log (@log)
|
add $4,$4,1 # make sure the jump shows in the log (@log)
|
|
|
# TODO traps in delay slots not supported yet
|
j syscall_jump_test2 # check if syscall works in delay slot of jump
|
#j syscall_jump_test2 # check if syscall works in delay slot of jump
|
syscall 0
|
#break 0
|
|
nop
|
nop
|
j syscall_continue
|
j syscall_continue
|
nop
|
nop
|
|
|
syscall_jump_test2:
|
syscall_jump_test2:
|
| Line 1408... |
Line 1414... |
j $DONE
|
j $DONE
|
nop
|
nop
|
|
|
# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
|
# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
|
setup_cache:
|
setup_cache:
|
lui $a0,0x0001 # Enable I-cache line invalidation
|
li $a0,0x00010002 # Enable I-cache line invalidation
|
mtc0 $a0,$12
|
mtc0 $a0,$12
|
|
|
# In order to invalidate a I-Cache line we have to write its tag number to
|
# In order to invalidate a I-Cache line we have to write its tag number to
|
# any address while bits CP0[12].17:16=01. The write will be executed as a
|
# any address while bits CP0[12].17:16=01. The write will be executed as a
|
# regular write too, as a side effect, so we need to choose a harmless
|
# regular write too, as a side effect, so we need to choose a harmless
|
| Line 1441... |
Line 1447... |
lw $zero,0($a0)
|
lw $zero,0($a0)
|
addi $a0,DCACHE_LINE_SIZE*4
|
addi $a0,DCACHE_LINE_SIZE*4
|
blt $a2,$a1,inv_d_cache_loop
|
blt $a2,$a1,inv_d_cache_loop
|
addi $a2,1
|
addi $a2,1
|
|
|
lui $a1,0x0002 # Leave with cache enabled
|
li $a1,0x00020002 # Leave with cache enabled
|
jr $ra
|
jr $ra
|
mtc0 $a1,$12
|
mtc0 $a1,$12
|
.set reorder
|
.set reorder
|
.end entry
|
.end entry
|
|
|
