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[/] [ion/] [trunk/] [src/] [opcodes/] [opcodes.s] - Diff between revs 165 and 203

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Line 20... Line 20...
# conditions. Instead, it performs the operations to be tested and relies on you
# conditions. Instead, it performs the operations to be tested and relies on you
# to compare the logs from the logic simulation and the software simulation.
# to compare the logs from the logic simulation and the software simulation.
# Test that work this way have been commented with this tag: "@log"
# Test that work this way have been commented with this tag: "@log"
#
#
#-------------------------------------------------------------------------------
#-------------------------------------------------------------------------------
# NOTE: NOPs have been inserted after load instructions.
# @note1: Hardware interrupt simulation
#
#
 
#   Hardware interrupts can be triggered by writing to a bank of debug
 
#   registers; you can trigger any or all of the 6 hardware interrupts of the
 
#   R3000 architecture (i.e. excluding the 2 SW interrupts), with any delay you
 
#   want, measured in instruction cycles, NOT clock cycles. You can make two or
 
#   more IRQs assert at the same time for test purposes.
 
#   Both the software simulator and the VHDL simulation test bench implement
 
#   these debug registers.
 
#   Note again that the delay is given in instruction cycles.
################################################################################
################################################################################
 
 
    #-- Set flags below to >0 to enable/disable test assembly ------------------
    #-- Set flags below to >0 to enable/disable test assembly ------------------
 
 
    .set TEST_UNALIGNED_LOADS, 0        # unaligned loads
    .set TEST_UNALIGNED_LOADS, 0        # unaligned loads
    .set TEST_UNALIGNED_STORES, 0       # unaligned stores
    .set TEST_UNALIGNED_STORES, 0       # unaligned stores
    .set TEST_BREAK, 1                  # BREAK instruction
    .set TEST_BREAK, 1                  # BREAK instruction
    # WARNING: the assembler expands div instructions, see 'as' manual
    # WARNING: the assembler expands div instructions, see 'as' manual
    .set TEST_DIV, 1                    # DIV* instructions
    .set TEST_DIV, 1                    # DIV* instructions
    .set TEST_MUL, 1                    # MUL* instructions
    .set TEST_MUL, 1                    # MUL* instructions
 
    .set TEST_BAD_OPCODES, 1            # Test opcode emulation trap
 
    .set TEST_TRAP_DELAY_EMU, 0         # Test emu of bad opcodes in delay slots
 
    .set TEST_HW_INTS, 1                # Test HW interrupts (@note1)
 
 
    .set USE_CACHE, 1                   # Initialize and enable cache
    .set USE_CACHE, 1                   # Initialize and enable cache
    .set EMU_MIPS32, 1                  # Emulates selected MIPS32 opcodes
 
 
 
    .set ICACHE_NUM_LINES, 256              # no. of lines in the I-Cache
    .set ICACHE_NUM_LINES, 256              # no. of lines in the I-Cache
    .set DCACHE_NUM_LINES, 256              # no. of lines in the D-Cache
    .set DCACHE_NUM_LINES, 256              # no. of lines in the D-Cache
    .set DCACHE_LINE_SIZE, 4                # D-Cache line size in words
    .set DCACHE_LINE_SIZE, 4                # D-Cache line size in words
 
 
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    bne     $k0,$k1,trap_invalid
    bne     $k0,$k1,trap_invalid
    nop
    nop
 
 
    # Unimplemented instruction
    # Unimplemented instruction
trap_unimplemented:
trap_unimplemented:
    .ifgt   EMU_MIPS32
    .ifgt   TEST_BAD_OPCODES
    # jump to mips32 opcode emulator with c0_cause in $k0
    # jump to mips32 opcode emulator with c0_cause in $k0
    j       opcode_emu
    j       opcode_emu
    nop
    nop
    .else
    .else
    # just do some simple arith so the opcode tester knows we were here
    # just do some simple arith so the opcode tester knows we were here
Line 1239... Line 1250...
    sb      $21,0($20)
    sb      $21,0($20)
 
 
    ######################################
    ######################################
    #Emulated MIPS32r2 Instructions
    #Emulated MIPS32r2 Instructions
    ######################################
    ######################################
    .ifgt   EMU_MIPS32
    .ifgt   TEST_BAD_OPCODES
    ori     $2,$0,'M'
    ori     $2,$0,'M'
    sb      $2,0($20)
    sb      $2,0($20)
    ori     $2,$0,'i'
    ori     $2,$0,'i'
    sb      $2,0($20)
    sb      $2,0($20)
    ori     $2,$0,'p'
    ori     $2,$0,'p'
Line 1368... Line 1379...
    addiu   $a1,$k0,'D'-0
    addiu   $a1,$k0,'D'-0
    sb      $a1,0($20)
    sb      $a1,0($20)
 
 
    sb      $23,0($20)
    sb      $23,0($20)
    sb      $21,0($20)
    sb      $21,0($20)
 
 
 
    # FIXME should test the bad opcode emulation in delay slots
    .endif
    .endif
 
 
 
 
 
 
    # Print 'Done'; the rest of the tests are for log matching only
    # Print 'Done'; the rest of the tests are for log matching only
    ori     $2,$0,'D'
    ori     $2,$0,'D'
    sb      $2,0($20)
    sb      $2,0($20)
    ori     $2,$0,'o'
    ori     $2,$0,'o'
    sb      $2,0($20)
    sb      $2,0($20)
Line 1562... Line 1577...
    bltz    $s4,test_b11
    bltz    $s4,test_b11
    nop
    nop
    ori     $v0,0x5503
    ori     $v0,0x5503
test_b11:
test_b11:
 
 
 
    #-- Hardware interrupts -----------------------------------------
 
test_hw_irq:
 
    .ifgt   TEST_HW_INTS
 
    li      $a0,0x20010000      # base address of debug reg block
 
 
 
    # Trigger IRQ_0 in 10 instruction cycles (@note1)
 
    #lhu     $a1,10              # load irq count down register...
 
    li      $a1,10
 
    sw      $a1,0($a0)
 
    lhu     $a2,20
 
test_hw_irq_0:
 
    bnez    $a2,test_hw_irq_0   # ...and wait for irq to trigger
 
    addiu   $a2,$a2,-1
 
 
 
    # When we arrive here, we should have executed the irq handler if
 
    # the irq worked properly, so check it.
 
 
 
    # FIXME incomplete code, stopped work here
 
 
 
    .endif
 
 
$DONE:
$DONE:
    j       $DONE
    j       $DONE               # End in an infinite loop
    nop
    nop
 
 
# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
# void setup_cache(void) -- invalidates all I- and D-Cache lines (uses no RAM)
setup_cache:
setup_cache:
    li      $a0,0x00010002      # Enable I-cache line invalidation
    li      $a0,0x00010002      # Enable I-cache line invalidation

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