| Line 49... |
Line 49... |
la $5, _end #$5 = .bss_end
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la $5, _end #$5 = .bss_end
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nop #no stack needed
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nop #no stack needed
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nop
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nop
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|
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b StartTest
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b StartTest
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nop #nops required to place ISR at 0x3c
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nop
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nop
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|
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OS_AsmPatchValue:
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#Code to place at address 0x3c
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lui $26, 0x1000
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ori $26, $26, 0x3c
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jr $26
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nop
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|
|
|
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# Trap handler address
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.org 0x3c
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.org 0x3c
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# FIXME assume exception is trap or break for the time being
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# We have three trap sources: syscall, break and unimplemented opcode
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InterruptVector: # Address=0x3c
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# Plus we have to account for a faulty cause code; that's 4 causes
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mfc0 $26,$14 # C0_EPC=14 (Exception PC)
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# Besides, we have to look out for the branch delay flag (BD)
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addi $26,$26,4 # skip trap instruction
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# We'll just increment $4 by a fixed constant depending on the cause
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jr $26
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# so we will not save any registers (there's no stack anyway)
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InterruptVector:
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mfc0 $k0,$13 # Get trap cause code
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andi $k0,$k0,0x01f
|
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ori $k1,$zero,0x8 # was it a syscall?
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beq $k0,$k1,trap_syscall
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addi $k1,$k1,0x1 # was it a break?
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beq $k0,$k1,trap_break
|
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addi $k1,$k1,0x1 # was it a bad opcode?
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|
bne $k0,$k1,trap_invalid
|
|
nop
|
|
|
|
# Unimplemented instruction
|
|
trap_unimplemented:
|
|
j trap_return
|
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add $4,$4,4
|
|
|
|
# Break instruction
|
|
trap_break:
|
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j trap_return
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add $4,$4,5
|
add $4,$4,5
|
|
|
|
# Syscall instruction
|
|
trap_syscall:
|
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j trap_return
|
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add $4,$4,6
|
|
|
|
# Invalid trap cause code, most likely hardware bug
|
|
trap_invalid:
|
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j trap_return
|
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add $4,$4,0xf
|
|
|
|
trap_return:
|
|
mfc0 $k1,$14 # C0_EPC=14 (Exception PC)
|
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mfc0 $k0,$13 # Get bit 31 (BD) from C0 cause register
|
|
srl $k0,31
|
|
andi $k0,$k0,1
|
|
bnez $k0,trap_return_delay_slot
|
|
addi $k1,$k1,4 # skip trap instruction
|
|
jr $k1
|
|
nop
|
|
trap_return_delay_slot:
|
|
addi $k1,$k1,4 # skip jump instruction too
|
|
jr $k1 # (we just added 8 to epc)
|
|
|
|
|
StartTest:
|
StartTest:
|
mtc0 $0,$12 # disable interrupts
|
mtc0 $0,$12 # disable interrupts
|
lui $20,0x2000 # serial port write address
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lui $20,0x2000 # serial port write address
|
ori $21,$0,'\n' # <CR> character
|
ori $21,$0,'\n' # <CR> character
|
ori $22,$0,'X' # 'X' letter
|
ori $22,$0,'X' # 'X' letter
|
| Line 84... |
Line 121... |
sb $23,0($20)
|
sb $23,0($20)
|
sb $21,0($20)
|
sb $21,0($20)
|
sb $23,0($20)
|
sb $23,0($20)
|
sb $21,0($20)
|
sb $21,0($20)
|
|
|
#Patch interrupt vector to 0x1000003c
|
|
la $5, OS_AsmPatchValue
|
|
sub $6,$5,0x1000
|
|
blez $6,NoPatch
|
|
nop
|
|
#lw $6, 0($5)
|
|
#sw $6, 0x3c($0)
|
|
#lw $6, 4($5)
|
|
#sw $6, 0x40($0)
|
|
#lw $6, 8($5)
|
|
#sw $6, 0x44($0)
|
|
#lw $6, 12($5)
|
|
#sw $6, 0x48($0)
|
|
NoPatch:
|
|
|
|
######################################
|
######################################
|
#Arithmetic Instructions
|
#Arithmetic Instructions
|
######################################
|
######################################
|
ArthmeticTest:
|
ArthmeticTest:
|
ori $2,$0,'A'
|
ori $2,$0,'A'
|
| Line 715... |
Line 737... |
add $4,$4,5
|
add $4,$4,5
|
|
|
break_jump_test1:
|
break_jump_test1:
|
add $4,$4,1 # make sure the jump shows in the log (@log)
|
add $4,$4,1 # make sure the jump shows in the log (@log)
|
|
|
# TODO traps in delay slots not supported yet
|
break 0 # check if store instruction is aborted
|
#j break_jump_test2# check if break works in delay slot of jump
|
sb $4,0($20)
|
#break 0
|
|
|
j break_jump_test2# check if break works in delay slot of jump
|
|
break 0
|
nop
|
nop
|
j break_continue
|
j break_continue
|
nop
|
nop
|
|
|
break_jump_test2:
|
break_jump_test2:
|
