OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [opcodes/] [readme.txt] - Diff between revs 66 and 197

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 66 Rev 197
Line 1... Line 1...
This is a basic opcode test bench which tries all supported opcodes. See the
This is a basic opcode test bench which tries all supported opcodes. See the
source comments. This code has been lifted whole from the Plasma project.
source comments. This code has been lifted whole from the Plasma project and
 
then gradually modified to its present state.
 
 
Build the program with:
This program can be simulated (both Modelsim and SW simulator) but it can't be
 
synthesized to a hardware demo (see makefiles). Only a 'sim' target is provided
make opcodes
in the makefile.
or
 
make opcodes_sim
 
 
 
Read ../readme.txt for some warnings on the makefile configuration.
 
 
 
 
 
It will build a vhdl test bench at /vhdl/tb/mips_tb2.vhdl (overwriting) that you
 
can try on your VHDL simulator with script sim_tb2.do. The provided script and
 
the VHDL code have some dependence on Modelsim, see project readme file.
 
 
 
 
 
The makefile will too bouild some bionaries that you can run in the software
 
simulator:
 
 
 
    slite --bram=opcodes.bin --xram=opcodes.data
 
 
 
 
 
This code can't be used on real hardware (i/o is far too simple).
 
 
 
WARNING: the gnu assembler expands DIV* instructions, inserting code that
WARNING: the gnu assembler expands DIV* instructions, inserting code that
handles division by zero. Bear that in mind when reading the listing file.
handles division by zero. Bear that in mind when reading the listing file.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.