| Line 41... |
Line 41... |
#include <stdint.h>
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#include <stdint.h>
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#include <string.h>
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#include <string.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <assert.h>
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#include <assert.h>
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#define R3000_ID (0x00000200)
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/** Set to !=0 to disable file logging (much faster simulation) */
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/** Set to !=0 to disable file logging (much faster simulation) */
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#define FILE_LOGGING_DISABLED (0)
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#define FILE_LOGGING_DISABLED (0)
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/** Define to enable cache simulation (unimplemented) */
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/** Define to enable cache simulation (unimplemented) */
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//#define ENABLE_CACHE
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//#define ENABLE_CACHE
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| Line 63... |
Line 65... |
uint8_t *mem;
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uint8_t *mem;
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char *area_name;
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char *area_name;
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} t_block;
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} t_block;
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#define NUM_MEM_BLOCKS (4)
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#define NUM_MEM_BLOCKS (4)
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#define NUM_MEM_MAPS (3)
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#define NUM_MEM_MAPS (4)
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/** Definition of a memory map */
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/** Definition of a memory map */
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/* FIXME i/o addresses missing, hardcoded */
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/* FIXME i/o addresses missing, hardcoded */
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typedef struct s_map {
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typedef struct s_map {
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t_block blocks[NUM_MEM_BLOCKS];
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t_block blocks[NUM_MEM_BLOCKS];
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| Line 94... |
Line 96... |
a 'mirror' effect. All of this simulates how the actual hardware works.
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a 'mirror' effect. All of this simulates how the actual hardware works.
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Make sure the blocks don't overlap or the scheme will fail.
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Make sure the blocks don't overlap or the scheme will fail.
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*/
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*/
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#define MAP_DEFAULT (0)
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#define MAP_DEFAULT (0)
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#define MAP_UCLINUX (1)
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#define MAP_UCLINUX_BRAM (1) /* debug only */
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#define MAP_SMALL (2)
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#define MAP_SMALL (2)
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#define MAP_UCLINUX (3)
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t_map memory_maps[NUM_MEM_MAPS] = {
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t_map memory_maps[NUM_MEM_MAPS] = {
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{/* Experimental memory map (default) */
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{/* Experimental memory map (default) */
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{/* Bootstrap BRAM, read only */
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{/* Bootstrap BRAM, read only */
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{VECTOR_RESET, 0x00004800, 0xf8000000, 1, NULL, "Boot BRAM"},
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{VECTOR_RESET, 0x00004800, 0xf8000000, 1, NULL, "Boot BRAM"},
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| Line 110... |
Line 113... |
/* external flash block */
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/* external flash block */
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{0xb0000000, 0x00040000, 0xf8000000, 0, NULL, "Flash"},
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{0xb0000000, 0x00040000, 0xf8000000, 0, NULL, "Flash"},
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}
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}
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},
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},
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{/* uClinux memory map */
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{/* uClinux memory map with bootstrap BRAM, debug only, to be removed */
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{/* Bootstrap BRAM, read only */
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{/* Bootstrap BRAM, read only */
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{VECTOR_RESET, 0x00001000, 0xf8000000, 1, NULL, "Boot BRAM"},
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{VECTOR_RESET, 0x00001000, 0xf8000000, 1, NULL, "Boot BRAM"},
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/* main external ram block */
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/* main external ram block */
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{0x80000000, 0x00200000, 0xf8000000, 0, NULL, "XRAM0"},
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{0x80000000, 0x00200000, 0xf8000000, 0, NULL, "XRAM0"},
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{0x00000000, 0x00400000, 0xf8000000, 0, NULL, "XRAM1"},
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{0x00000000, 0x00400000, 0xf8000000, 0, NULL, "XRAM1"},
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| Line 132... |
Line 135... |
{0x80000000, 0x00001000, 0xf8000000, 0, NULL, "XRAM1"},
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{0x80000000, 0x00001000, 0xf8000000, 0, NULL, "XRAM1"},
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/* external flash block */
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/* external flash block */
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{0xb0000000, 0x00040000, 0xf8000000, 0, NULL, "Flash"},
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{0xb0000000, 0x00040000, 0xf8000000, 0, NULL, "Flash"},
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}
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}
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},
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},
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{/* uClinux memory map with FLASH and XRAM */
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{/* Flash mapped at two different addresses is actually meant to be
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a single chip (note they have the same size). */
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/* E.g. put the bootloader at 0xbfc00000 and the romfs at 0xb0020000;
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chip offsets will be 0x0 and 0x20000. */
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/* Don't forget there's no address translation here. */
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{0xbfc00000, 0x00400000, 0xf8000000, 1, NULL, "Flash (bootloader)"},
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{0xb0000000, 0x00400000, 0xf8000000, 1, NULL, "Flash (romfs)"},
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/* main external ram block (kernal & user areas ) */
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{0x80000000, 0x00200000, 0xf8000000, 0, NULL, "XRAM (kernel)"},
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{0x00000000, 0x00400000, 0xf8000000, 0, NULL, "XRAM (user)"},
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}
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},
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};
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};
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/*---- end of system parameters ----------------------------------------------*/
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/*---- end of system parameters ----------------------------------------------*/
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| Line 272... |
Line 289... |
unsigned int next; /**< internal queue head pointer */
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unsigned int next; /**< internal queue head pointer */
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FILE *log; /**< text log file or NULL */
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FILE *log; /**< text log file or NULL */
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int log_triggered; /**< !=0 if log has been triggered */
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int log_triggered; /**< !=0 if log has been triggered */
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uint32_t log_trigger_address; /**< */
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uint32_t log_trigger_address; /**< */
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int pr[32]; /**< last value of register bank */
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int pr[32]; /**< last value of register bank */
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int hi, lo, epc; /**< last value of internal regs */
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int hi, lo, epc, status; /**< last value of internal regs */
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} t_trace;
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} t_trace;
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typedef struct s_state {
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typedef struct s_state {
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unsigned failed_assertions; /**< assertion bitmap */
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unsigned failed_assertions; /**< assertion bitmap */
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unsigned faulty_address; /**< addr that failed assertion */
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unsigned faulty_address; /**< addr that failed assertion */
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| Line 346... |
Line 363... |
void log_cycle(t_state *s);
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void log_cycle(t_state *s);
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void log_read(t_state *s, int full_address, int word_value, int size, int log);
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void log_read(t_state *s, int full_address, int word_value, int size, int log);
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void log_failed_assertions(t_state *s);
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void log_failed_assertions(t_state *s);
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uint32_t log_enabled(t_state *s);
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uint32_t log_enabled(t_state *s);
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void trigger_log(t_state *s);
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void trigger_log(t_state *s);
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void print_opcode_fields(uint32_t opcode);
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int32_t parse_cmd_line(uint32_t argc, char **argv, t_args *args);
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int32_t parse_cmd_line(uint32_t argc, char **argv, t_args *args);
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void usage(void);
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void usage(void);
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/* CPU model */
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/* CPU model */
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| Line 876... |
Line 894... |
case 0x32:/*TLT*/ break;
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case 0x32:/*TLT*/ break;
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case 0x33:/*TLTU*/ break;
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case 0x33:/*TLTU*/ break;
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case 0x34:/*TEQ*/ break;
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case 0x34:/*TEQ*/ break;
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case 0x36:/*TNE*/ break;
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case 0x36:/*TNE*/ break;
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default: printf("ERROR0(*0x%x~0x%x)\n", s->pc, opcode);
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default: printf("ERROR0(*0x%x~0x%x)\n", s->pc, opcode);
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/* FIXME should trap unknown opcode */
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s->wakeup=1;
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s->wakeup=1;
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}
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}
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break;
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break;
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case 0x01:/*REGIMM*/
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case 0x01:/*REGIMM*/
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switch(rt){
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switch(rt){
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| Line 908... |
Line 927... |
case 0x0c:/*ANDI*/ r[rt]=r[rs]&imm; break;
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case 0x0c:/*ANDI*/ r[rt]=r[rs]&imm; break;
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case 0x0d:/*ORI*/ r[rt]=r[rs]|imm; break;
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case 0x0d:/*ORI*/ r[rt]=r[rs]|imm; break;
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case 0x0e:/*XORI*/ r[rt]=r[rs]^imm; break;
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case 0x0e:/*XORI*/ r[rt]=r[rs]^imm; break;
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case 0x0f:/*LUI*/ r[rt]=(imm<<16); break;
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case 0x0f:/*LUI*/ r[rt]=(imm<<16); break;
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case 0x10:/*COP0*/
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case 0x10:/*COP0*/
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if(s->status & 0x02){ /* kernel mode? */
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if((opcode & (1<<23)) == 0){ //move from CP0 (mfc0)
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if((opcode & (1<<23)) == 0){ //move from CP0 (mfc0)
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switch(rd){
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switch(rd){
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case 12: r[rt]=s->status & 0xffff; break;
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case 12: r[rt]=s->status & 0x0000003f; break;
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case 13: r[rt]=s->cp0_cause; break;
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case 13: r[rt]=s->cp0_cause; break;
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case 14: r[rt]=s->epc; break;
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case 14: r[rt]=s->epc; break;
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case 15: r[rt]=0x00000200; break;
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case 15: r[rt]=R3000_ID; break;
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default:
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default:
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//printf("mfco [%02d]\n", rd);
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//printf("mfco [%02d]\n", rd);
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break;
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break;
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}
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}
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}
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}
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else{ //move to CP0 (mtc0)
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else{ //move to CP0 (mtc0)
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/* FIXME check CF= reg address */
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/* FIXME check CF= reg address */
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s->status=r[rt];
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s->status=r[rt] & 0x0003003f; /* mask W/O bits */
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if(s->processId && (r[rt]&2)){
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if(s->processId && (r[rt]&2)){
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s->userMode|=r[rt]&2;
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s->userMode|=r[rt]&2;
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//printf("CpuStatus=%d %d %d\n", r[rt], s->status, s->userMode);
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//printf("CpuStatus=%d %d %d\n", r[rt], s->status, s->userMode);
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//s->wakeup = 1;
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//s->wakeup = 1;
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//printf("pc=0x%x\n", epc);
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//printf("pc=0x%x\n", epc);
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}
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}
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}
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}
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}
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else{
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/* tried to execute mtc* or mfc* in user mode: trap */
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trap_cause = 11; /* unavailable coprocessor */
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s->exceptionId=1;
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}
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break;
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break;
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case 0x11:/*COP1*/ unimplemented(s,"COP1");
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case 0x11:/*COP1*/ unimplemented(s,"COP1");
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break;
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break;
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// case 0x12:/*COP2*/ break;
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// case 0x12:/*COP2*/ break;
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// case 0x13:/*COP3*/ break;
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// case 0x13:/*COP3*/ break;
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| Line 993... |
Line 1019... |
// case 0x3f:/*SDC3*/ break;
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// case 0x3f:/*SDC3*/ break;
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default:
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default:
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;
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;
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/* FIXME should trap unimplemented opcodes */
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/* FIXME should trap unimplemented opcodes */
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/* FIXME newlib */
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/* FIXME newlib */
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printf("ERROR2 address=0x%x opcode=0x%x\n", s->pc, opcode);
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printf("ERROR2 address=0x%x opcode=0x%x -- ", epc, opcode);
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print_opcode_fields(opcode);
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printf("\n");
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s->wakeup=1;
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s->wakeup=1;
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}
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}
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/* adjust next PC if this was a ajump instruction */
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/* adjust next PC if this was a ajump instruction */
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s->pc_next += (branch || lbranch == 1) ? imm_shift : 0;
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s->pc_next += (branch || lbranch == 1) ? imm_shift : 0;
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| Line 1014... |
Line 1042... |
/* load delay slots not simulated */
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/* load delay slots not simulated */
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/* Handle exceptions */
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/* Handle exceptions */
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if(s->exceptionId){
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if(s->exceptionId){
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r[rt] = rSave;
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r[rt] = rSave;
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s->cp0_cause = (s->delay_slot & 0x1) << 31 | (trap_cause & 0x1f);
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/* set cause field ... */
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s->cp0_cause = (s->delay_slot & 0x1) << 31 | (trap_cause & 0x1f) << 2;
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/* ...save previous KU/IE flags in SR... */
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s->status = (s->status & 0xffffffc3) | ((s->status & 0x0f) << 2);
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/* ...and raise KU(EXL) kernel mode flag */
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s->status |= 0x02;
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/* adjust epc if we (i.e. the victim instruction) are in a delay slot */
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/* adjust epc if we (i.e. the victim instruction) are in a delay slot */
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if(s->delay_slot){
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if(s->delay_slot){
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epc = epc - 4;
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epc = epc - 4;
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}
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}
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s->epc = epc;
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s->epc = epc;
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| Line 1040... |
Line 1073... |
the next instruction will be in a delay slot. Remember it. */
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the next instruction will be in a delay slot. Remember it. */
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delay_slot = ((lbranch==1) || branch || delay_slot);
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delay_slot = ((lbranch==1) || branch || delay_slot);
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s->delay_slot = delay_slot;
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s->delay_slot = delay_slot;
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}
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}
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/** Print opcode fields for easier debugging */
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void print_opcode_fields(uint32_t opcode){
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uint32_t field;
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field = (opcode >> 26)&0x3f;
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printf("%02x:", field);
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field = (opcode >> 21)&0x1f;
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printf("%02x:", field);
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field = (opcode >> 16)&0x1f;
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printf("%02x:", field);
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field = (opcode >> 11)&0x1f;
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printf("%02x:", field);
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field = (opcode >> 6)&0x1f;
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printf("%02x:", field);
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field = (opcode >> 0)&0x3f;
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printf("%02x", field);
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}
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/** Dump CPU state to console */
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/** Dump CPU state to console */
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void show_state(t_state *s){
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void show_state(t_state *s){
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int i,j;
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int i,j;
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printf("pid=%d userMode=%d, epc=0x%x\n", s->processId, s->userMode, s->epc);
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printf("pid=%d userMode=%d, epc=0x%x\n", s->processId, s->userMode, s->epc);
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printf("hi=0x%08x lo=0x%08x\n", s->hi, s->lo);
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printf("hi=0x%08x lo=0x%08x\n", s->hi, s->lo);
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| Line 1370... |
Line 1422... |
if(s->hi != s->t.hi){
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if(s->hi != s->t.hi){
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//fprintf(s->t.log, "(%08X) [HI]=%08X\n", log_pc, s->hi);
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//fprintf(s->t.log, "(%08X) [HI]=%08X\n", log_pc, s->hi);
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}
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}
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s->t.hi = s->hi;
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s->t.hi = s->hi;
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/* */
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/* Catch changes in EPC by direct write (mtc0) and by exception */
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/* FIXME epc may change by direct write too, handle case */
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if(s->epc != s->t.epc){
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if(s->epc != s->t.epc){
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fprintf(s->t.log, "(%08X) [EP]=%08X\n", log_pc, s->epc);
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fprintf(s->t.log, "(%08X) [EP]=%08X\n", log_pc, s->epc);
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}
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}
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s->t.epc = s->epc;
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s->t.epc = s->epc;
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if(s->status != s->t. status){
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fprintf(s->t.log, "(%08X) [SR]=%08X\n", log_pc, s->status);
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}
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s->t.status = s->status;
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}
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}
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}
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}
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/** Frees debug buffers and closes log file */
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/** Frees debug buffers and closes log file */
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void close_trace_buffer(t_state *s){
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void close_trace_buffer(t_state *s){
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| Line 1435... |
Line 1491... |
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void reset_cpu(t_state *s){
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void reset_cpu(t_state *s){
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s->pc = VECTOR_RESET; /* reset start vector */
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s->pc = VECTOR_RESET; /* reset start vector */
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s->delay_slot = 0;
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s->delay_slot = 0;
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s->failed_assertions = 0; /* no failed assertions pending */
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s->failed_assertions = 0; /* no failed assertions pending */
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s->status = 0x02; /* kernel mode, interrupts disabled */
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/* init trace struct to prevent spurious logs */
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s->t.status = s->status;
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}
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}
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void unimplemented(t_state *s, const char *txt){
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void unimplemented(t_state *s, const char *txt){
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/* FIXME unimplemented opcode trap */
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/* FIXME unimplemented opcode trap */
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printf("UNIMPLEMENTED: %s\n", txt);
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printf("UNIMPLEMENTED: %s\n", txt);
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