| Line 275... |
Line 275... |
/* FIXME Refactor HW system params */
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/* FIXME Refactor HW system params */
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#define DBG_REGS (0x20010000)
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#define DBG_REGS (0x20010000)
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#define UART_WRITE (0x20000000)
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#define UART_WRITE (0x20000000)
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#define UART_READ (0x20000000)
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#define UART_READ (0x20000000)
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#define UART_STATUS (0x20000004)
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#define TIMER_READ (0x20000100)
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#define TIMER_READ (0x20000100)
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#define DEFAULT_TIMER_PRESCALER (50)
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#define DEFAULT_TIMER_PRESCALER (50)
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/* FIXME The following addresses are remnants of Plasma to be removed */
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/* FIXME The following addresses are remnants of Plasma to be removed */
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| Line 287... |
Line 288... |
#define CONFIG_REG 0x20000070
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#define CONFIG_REG 0x20000070
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#define MMU_PROCESS_ID 0x20000080
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#define MMU_PROCESS_ID 0x20000080
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#define MMU_FAULT_ADDR 0x20000090
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#define MMU_FAULT_ADDR 0x20000090
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#define MMU_TLB 0x200000a0
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#define MMU_TLB 0x200000a0
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#define IRQ_UART_READ_AVAILABLE 0x001
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#define IRQ_UART_READ_AVAILABLE 0x002
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#define IRQ_UART_WRITE_AVAILABLE 0x002
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#define IRQ_UART_WRITE_AVAILABLE 0x001
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#define IRQ_COUNTER18_NOT 0x004
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#define IRQ_COUNTER18_NOT 0x004
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#define IRQ_COUNTER18 0x008
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#define IRQ_COUNTER18 0x008
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#define IRQ_MMU 0x200
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#define IRQ_MMU 0x200
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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| Line 332... |
Line 333... |
uint32_t breakpoint; /**< BP address of 0xffffffff */
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uint32_t breakpoint; /**< BP address of 0xffffffff */
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int delay_slot; /**< !=0 if prev. instruction was a branch */
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int delay_slot; /**< !=0 if prev. instruction was a branch */
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uint32_t instruction_ctr; /**< # of instructions executed since reset */
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uint32_t instruction_ctr; /**< # of instructions executed since reset */
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uint32_t inst_ctr_prescaler; /**< Prescaler counter for instruction ctr. */
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uint32_t inst_ctr_prescaler; /**< Prescaler counter for instruction ctr. */
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uint32_t debug_regs[16]; /**< Rd/wr debug registers */
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int r[32];
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int r[32];
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int opcode;
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int opcode;
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int pc, pc_next, epc;
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int pc, pc_next, epc;
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uint32_t op_addr; /**< address of opcode being simulated */
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uint32_t op_addr; /**< address of opcode being simulated */
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| Line 451... |
Line 453... |
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/* Hardware simulation */
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/* Hardware simulation */
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int mem_read(t_state *s, int size, unsigned int address, int log);
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int mem_read(t_state *s, int size, unsigned int address, int log);
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void mem_write(t_state *s, int size, unsigned address, unsigned value, int log);
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void mem_write(t_state *s, int size, unsigned address, unsigned value, int log);
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void debug_reg_write(t_state *s, uint32_t address, uint32_t data);
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void debug_reg_write(t_state *s, uint32_t address, uint32_t data);
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int debug_reg_read(t_state *s, int size, unsigned int address);
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void start_load(t_state *s, uint32_t addr, int rt, int data);
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void start_load(t_state *s, uint32_t addr, int rt, int data);
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uint32_t simulate_hw_irqs(t_state *s);
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uint32_t simulate_hw_irqs(t_state *s);
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/*---- Local functions -------------------------------------------------------*/
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/*---- Local functions -------------------------------------------------------*/
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Line 535... |
/** Read memory, optionally logging */
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/** Read memory, optionally logging */
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int mem_read(t_state *s, int size, unsigned int address, int log){
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int mem_read(t_state *s, int size, unsigned int address, int log){
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unsigned int value=0, word_value=0, i, ptr;
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unsigned int value=0, word_value=0, i, ptr;
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unsigned int full_address = address;
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unsigned int full_address = address;
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/* Handle access to debug register block */
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if((address&0xffff0000)==(DBG_REGS&0xffff0000)){
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return debug_reg_read(s, size, address);
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}
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s->irqStatus |= IRQ_UART_WRITE_AVAILABLE;
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s->irqStatus |= IRQ_UART_WRITE_AVAILABLE;
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switch(address){
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switch(address){
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case UART_READ:
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case UART_READ:
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/* FIXME Take input from text file */
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/* FIXME Take input from text file */
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/* Wait for incoming character */
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while(!kbhit());
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while(!kbhit());
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HWMemory[0] = getch();
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HWMemory[0] = getch();
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//s->irqStatus &= ~IRQ_UART_READ_AVAILABLE; //clear bit
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//s->irqStatus &= ~IRQ_UART_READ_AVAILABLE; //clear bit
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printf("%c", HWMemory[0]);
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printf("%c", HWMemory[0]);
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return (HWMemory[0] << 24) | 0x03;
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return HWMemory[0];
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case UART_STATUS:
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/* Hardcoded status bits: tx and rx available */
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return IRQ_UART_WRITE_AVAILABLE | IRQ_UART_READ_AVAILABLE;
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case TIMER_READ:
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case TIMER_READ:
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printf("TIMER = %10d\n", s->instruction_ctr);
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printf("TIMER = %10d\n", s->instruction_ctr);
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return s->instruction_ctr;
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return s->instruction_ctr;
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break;
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break;
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case IRQ_MASK:
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case IRQ_MASK:
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| Line 634... |
Line 646... |
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//log_read(s, full_address, value, size, log);
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//log_read(s, full_address, value, size, log);
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return(value);
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return(value);
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}
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}
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int debug_reg_read(t_state *s, int size, unsigned int address){
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/* FIXME should mirror debug registers 0..3 */
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return s->debug_regs[(address >> 2)&0x0f];
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}
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/** Write to debug register */
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/** Write to debug register */
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void debug_reg_write(t_state *s, uint32_t address, uint32_t data){
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void debug_reg_write(t_state *s, uint32_t address, uint32_t data){
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if((address>= 0x0000f000) && (address < 0x0000f008)){
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if((address>= 0x0000f000) && (address < 0x0000f008)){
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/* HW interrupt trigger register */
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/* HW interrupt trigger register */
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| Line 645... |
Line 663... |
printf("DEBUG REG[%04x]=%08x\n", address & 0xffff, data);
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printf("DEBUG REG[%04x]=%08x\n", address & 0xffff, data);
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}
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}
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else{
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else{
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/* all other registers are used for display (like LEDs) */
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/* all other registers are used for display (like LEDs) */
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printf("DEBUG REG[%04x]=%08x\n", address & 0xffff, data);
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printf("DEBUG REG[%04x]=%08x\n", address & 0xffff, data);
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s->debug_regs[(address >> 2)&0x0f] = data;
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}
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}
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}
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}
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/** Write to memory, including simulated i/o */
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/** Write to memory, including simulated i/o */
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void mem_write(t_state *s, int size, unsigned address, unsigned value, int log){
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void mem_write(t_state *s, int size, unsigned address, unsigned value, int log){
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