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--------------------------------------------------------------------------------
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-- Synthesizable MPU -- CPU + cache + bootstrap ROM (BRAM) + UART
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--------------------------------------------------------------------------------
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-- Copyright (C) 2011 Jose A. Ruiz
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use work.code_rom_pkg.all;
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entity mips_mpu is
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generic (
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CLOCK_FREQ : integer := 50000000;
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SRAM_ADDR_SIZE : integer := 17
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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interrupt : in std_logic_vector(7 downto 0);
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-- interface to FPGA i/o devices
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_data : out std_logic_vector(31 downto 0);
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io_rd_vma : out std_logic;
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io_byte_we : out std_logic_vector(3 downto 0);
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
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sram_data_wr : out std_logic_vector(15 downto 0);
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sram_data_rd : in std_logic_vector(15 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_oe_n : out std_logic;
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-- UART
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uart_rxd : in std_logic;
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uart_txd : out std_logic;
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-- Debug info
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debug_info : out t_debug_info
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);
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end; --entity mips_mpu
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architecture rtl of mips_mpu is
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-- interface cpu-cache
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signal cpu_data_addr : t_word;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd : t_word;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_cache_enable : std_logic;
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signal unmapped_access : std_logic;
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-- interface to i/o
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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-- interface to UARTs
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signal uart_rd_word : t_word;
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_write : std_logic;
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signal uart_read : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_data_rx : std_logic_vector(7 downto 0);
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-- interface to bootstrap code BRAM
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-- NOTE: 'write' signals are a remnant from a previous version, to be removed
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signal bram_rd_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_rd_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_byte_we : std_logic_vector(3 downto 0);
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--------------------------------------------------------------------------------
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begin
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cpu: entity work.mips_cpu
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port map (
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interrupt => interrupt,
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data_addr => cpu_data_addr,
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data_rd_vma => cpu_data_rd_vma,
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data_rd => cpu_data_rd,
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code_rd_addr=> cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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mem_wait => cpu_mem_wait,
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cache_enable=> cpu_cache_enable,
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ic_invalidate=>cpu_ic_invalidate,
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clk => clk,
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reset => reset
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);
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cache: entity work.mips_cache
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generic map (
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BRAM_ADDR_SIZE => CODE_BRAM_ADDR_SIZE,
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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)
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port map (
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clk => clk,
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reset => reset,
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-- Interface to CPU core
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data_addr => cpu_data_addr,
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data_rd => cpu_data_rd,
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data_rd_vma => cpu_data_rd_vma,
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code_rd_addr => cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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mem_wait => cpu_mem_wait,
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cache_enable => cpu_cache_enable,
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ic_invalidate => cpu_ic_invalidate,
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unmapped => unmapped_access,
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-- interface to FPGA i/o devices
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io_rd_data => mpu_io_rd_data,
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io_wr_data => mpu_io_wr_data,
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io_rd_addr => mpu_io_rd_addr,
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io_wr_addr => mpu_io_wr_addr,
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io_rd_vma => mpu_io_rd_vma,
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io_byte_we => mpu_io_byte_we,
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-- interface to synchronous 32-bit-wide FPGA BRAM
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bram_rd_data => bram_rd_data,
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bram_wr_data => bram_wr_data,
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bram_rd_addr => bram_rd_addr,
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bram_wr_addr => bram_wr_addr,
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bram_byte_we => bram_byte_we,
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-- interface to asynchronous 16-bit-wide external SRAM
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sram_address => sram_address,
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sram_data_rd => sram_data_rd,
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sram_data_wr => sram_data_wr,
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sram_byte_we_n => sram_byte_we_n,
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sram_oe_n => sram_oe_n
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);
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--------------------------------------------------------------------------------
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-- BRAM interface
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fpga_ram_block:
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process(clk)
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begin
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if clk'event and clk='1' then
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bram_rd_data <= code_bram(conv_integer(unsigned(bram_rd_addr)));
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end if;
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end process fpga_ram_block;
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--------------------------------------------------------------------------------
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-- Debug stuff
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-- Register some debug signals. These are meant to be connected to LEDs on a
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-- dev board, or maybe to logic analyzer probes. They are not useful once
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-- the core is fully debugged.
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debug_info_register:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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debug_info.unmapped_access <= '0';
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else
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if unmapped_access='1' then
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-- This flag will be asserted permanently after any kind of
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-- unmapped access (code, data read or data write).
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debug_info.unmapped_access <= '1';
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end if;
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end if;
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debug_info.cache_enabled <= cpu_cache_enable;
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end if;
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end process debug_info_register;
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--------------------------------------------------------------------------------
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serial_rx : entity work.rs232_rx
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generic map (
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CLOCK_FREQ => CLOCK_FREQ
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)
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port map(
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rxd => uart_rxd,
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data_rx => uart_data_rx,
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rx_rdy => uart_rx_rdy,
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read_rx => uart_read_rx,
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clk => clk,
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reset => reset
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);
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-- '1'-> Read some UART register (0x2---0---)
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uart_read <= '1'
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when mpu_io_rd_vma='1' and
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mpu_io_rd_addr(31 downto 28)=X"2" and
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mpu_io_rd_addr(15 downto 12)=X"0"
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else '0';
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-- '1'-> Read UART Rx data (0x2---0-0-)
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-- (This signal clears the RX 1-char buffer)
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uart_read_rx <= '1'
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when uart_read='1' and
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mpu_io_rd_addr( 7 downto 4)=X"0"
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else '0';
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-- '1'-> Write UART Tx register (trigger UART Tx) (0x20000000)
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uart_write <= '1'
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when mpu_io_byte_we/="0000" and
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mpu_io_wr_addr(31 downto 28)=X"2" and
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mpu_io_wr_addr(15 downto 12)=X"0"
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else '0';
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serial_tx : entity work.rs232_tx
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generic map (
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CLOCK_FREQ => CLOCK_FREQ
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)
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port map(
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clk => clk,
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reset => reset,
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rdy => uart_tx_rdy,
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load => uart_write,
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data_i => mpu_io_wr_data(7 downto 0),
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txd => uart_txd
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);
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-- Both UART rd addresses 000 and 020 read the same word (save a mux), but only
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-- address 000 clears the rx buffer.
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uart_rd_word <= uart_data_rx & X"00000" & "00" & uart_tx_rdy & uart_rx_rdy;
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-- IO Rd mux: either the UART data/status word od the IO coming from outside
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mpu_io_rd_data <=
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uart_rd_word when mpu_io_rd_addr(15 downto 12)=X"0" else
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io_rd_data;
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-- io_rd_data
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io_rd_addr <= mpu_io_rd_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_data <= mpu_io_wr_data;
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io_rd_vma <= mpu_io_rd_vma;
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io_byte_we <= mpu_io_byte_we;
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end architecture rtl;
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