| Line 117... |
Line 117... |
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-- UART
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-- UART
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uart_rxd : in std_logic;
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uart_rxd : in std_logic;
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uart_txd : out std_logic;
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uart_txd : out std_logic;
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-- I/O ports
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p0_out : out std_logic_vector(31 downto 0);
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p1_in : in std_logic_vector(31 downto 0);
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-- Debug info register output
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-- Debug info register output
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debug_info : out t_debug_info
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debug_info : out t_debug_info
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);
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);
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end; --entity mips_soc
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end; --entity mips_soc
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| Line 151... |
Line 155... |
-- Interface to UARTs
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-- Interface to UARTs
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signal uart_ce : std_logic;
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signal uart_ce : std_logic;
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signal uart_irq : std_logic;
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signal uart_irq : std_logic;
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signal uart_rd_byte : std_logic_vector(7 downto 0);
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signal uart_rd_byte : std_logic_vector(7 downto 0);
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-- I/O registers
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signal p0_reg : std_logic_vector(31 downto 0);
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signal p1_reg : std_logic_vector(31 downto 0);
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signal gpio_rd_data : std_logic_vector(31 downto 0);
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-- Bootstrap code BRAM
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-- Bootstrap code BRAM
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constant BOOT_BRAM_ADDR_SIZE : integer := log2(BOOT_BRAM_SIZE);
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constant BOOT_BRAM_ADDR_SIZE : integer := log2(BOOT_BRAM_SIZE);
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subtype t_boot_bram_address is std_logic_vector(BOOT_BRAM_ADDR_SIZE-1 downto 0);
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subtype t_boot_bram_address is std_logic_vector(BOOT_BRAM_ADDR_SIZE-1 downto 0);
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-- Boot BRAM, initialized with constant object code table
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-- Boot BRAM, initialized with constant object code table
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signal boot_bram : t_word_table(0 to BOOT_BRAM_SIZE-1) :=
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signal boot_bram : t_word_table(0 to BOOT_BRAM_SIZE-1) :=
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| Line 313... |
Line 322... |
mpu_io_wr_addr(15 downto 12)=X"0")
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mpu_io_wr_addr(15 downto 12)=X"0")
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else '0';
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else '0';
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- GPIO registers
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gpio_output_registers:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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p0_reg <= (others => '0');
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else
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if mpu_io_wr_addr(19 downto 12)=X"01" then
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if mpu_io_byte_we(0)='1' then
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p0_reg( 7 downto 0) <= mpu_io_wr_data( 7 downto 0);
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end if;
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if mpu_io_byte_we(1)='1' then
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p0_reg(15 downto 8) <= mpu_io_wr_data(15 downto 8);
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end if;
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if mpu_io_byte_we(2)='1' then
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p0_reg(23 downto 16) <= mpu_io_wr_data(23 downto 16);
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end if;
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if mpu_io_byte_we(3)='1' then
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p0_reg(31 downto 24) <= mpu_io_wr_data(31 downto 24);
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end if;
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end if;
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end if;
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end if;
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end process gpio_output_registers;
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p0_out <= p0_reg;
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gpio_input_registers:
|
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process(clk)
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begin
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-- Note the input register needs no reset value.
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if clk'event and clk='1' then
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p1_reg <= p1_in;
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end if;
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end process gpio_input_registers;
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with mpu_io_rd_addr(2) select gpio_rd_data <=
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p0_reg when '0',
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p1_reg when others;
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--------------------------------------------------------------------------------
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-- I/O port multiplexor
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-- I/O port multiplexor
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|
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-- IO Rd mux: either the UART data/status word or the IO coming from outside
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-- IO Rd mux: either the UART data/status word or the IO coming from outside
|
mpu_io_rd_data <=
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with mpu_io_rd_addr(19 downto 12) select mpu_io_rd_data <=
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X"000000" & uart_rd_byte when mpu_io_rd_addr(19 downto 12)=X"00" else
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X"000000" & uart_rd_byte when X"00",
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io_rd_data;
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gpio_rd_data when X"01",
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io_rd_data when others;
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-- io_rd_data
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-- io_rd_data
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io_rd_addr <= mpu_io_rd_addr;
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io_rd_addr <= mpu_io_rd_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_data <= mpu_io_wr_data;
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io_wr_data <= mpu_io_wr_data;
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