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--##############################################################################
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--##############################################################################
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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--##############################################################################
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--##############################################################################
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-- This module is little more than a wrapper around the CPU and its memories.
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-- This module is little more than a wrapper around the CPU and its memories.
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-- Synthesize with 'balanced' optimization for best results.
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--------------------------------------------------------------------------------
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-- NOTE: See note at bottom of file about optional use of PLL.
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--##############################################################################
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--##############################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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-- (Many of the board's i/o devices will go unused in this demo)
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-- (Many of the board's i/o devices will go unused in this demo)
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entity c2sb_demo is
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entity c2sb_demo is
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port (
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port (
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-- ***** Clocks
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-- ***** Clocks
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clk_50MHz : in std_logic;
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clk_50MHz : in std_logic;
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clk_27MHz : in std_logic;
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-- ***** Flash 4MB
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-- ***** Flash 4MB
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flash_addr : out std_logic_vector(21 downto 0);
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flash_addr : out std_logic_vector(21 downto 0);
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flash_data : in std_logic_vector(7 downto 0);
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flash_data : in std_logic_vector(7 downto 0);
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flash_oe_n : out std_logic;
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flash_oe_n : out std_logic;
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Line 64... |
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architecture minimal of c2sb_demo is
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architecture minimal of c2sb_demo is
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--##############################################################################
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--##############################################################################
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--
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-- Parameters
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-- Address size (FIXME: not tested with other values)
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constant SRAM_ADDR_SIZE : integer := 32;
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constant SRAM_ADDR_SIZE : integer := 32;
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-- Clock rate selection (affects UART configuration)
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-- Acceptable values: {27000000, 50000000, 45000000(pll config)}
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constant CLOCK_FREQ : integer := 50000000;
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--##############################################################################
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--##############################################################################
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-- RS232 interface signals
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-- RS232 interface signals
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signal rx_rdy : std_logic;
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signal rx_rdy : std_logic;
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signal tx_rdy : std_logic;
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signal tx_rdy : std_logic;
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Line 97... |
signal sd_cmd_reg : std_logic;
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signal sd_cmd_reg : std_logic;
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signal sd_do_reg : std_logic;
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signal sd_do_reg : std_logic;
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-- CPU access to hex display
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-- CPU access to hex display
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signal reg_display : std_logic_vector(15 downto 0);
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signal reg_display : std_logic_vector(31 downto 0);
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--##############################################################################
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--##############################################################################
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-- DE-1 board interface signals
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-- DE-1 board interface signals
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-- Synchronization FF chain for asynchronous reset input
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-- Synchronization FF chain for asynchronous reset input
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signal reset_sync : std_logic_vector(2 downto 0);
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signal reset_sync : std_logic_vector(3 downto 0);
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-- Reset pushbutton debouncing logic
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subtype t_debouncer is integer range 0 to CLOCK_FREQ;
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constant DEBOUNCING_DELAY : t_debouncer := 500;
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signal debouncing_counter : t_debouncer := (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
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-- Quad 7-segment display (non multiplexed) & LEDS
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-- Quad 7-segment display (non multiplexed) & LEDS
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signal display_data : std_logic_vector(15 downto 0);
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signal display_data : std_logic_vector(15 downto 0);
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signal reg_gleds : std_logic_vector(7 downto 0);
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signal reg_gleds : std_logic_vector(7 downto 0);
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-- Clock & reset signals
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-- Clock & reset signals
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signal clk_1hz : std_logic;
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signal clk_1hz : std_logic;
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signal clk_master : std_logic;
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signal clk_master : std_logic;
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signal counter_1hz : std_logic_vector(25 downto 0);
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signal counter_1hz : std_logic_vector(25 downto 0);
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signal reset : std_logic;
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signal reset : std_logic;
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-- Master clock signal
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signal clk : std_logic;
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signal clk : std_logic;
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-- Clock from PLL, is a PLL is used
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signal clk_pll : std_logic;
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-- '1' when PLL is locked or when no PLL is used
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signal pll_locked : std_logic;
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-- Altera PLL component declaration (in case it's used)
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-- Note that the MegaWizard component needs to be called 'pll' or the component
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-- name should be changed in this file.
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--component pll
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-- port (
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-- areset : in std_logic := '0';
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-- inclk0 : in std_logic := '0';
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-- c0 : out std_logic ;
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-- locked : out std_logic
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-- );
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--end component;
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-- SD control signals
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-- SD control signals
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signal sd_in : std_logic;
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signal sd_in : std_logic;
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signal reg_sd_dout : std_logic;
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signal reg_sd_dout : std_logic;
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signal reg_sd_clk : std_logic;
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signal reg_sd_clk : std_logic;
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Line 196... |
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begin
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begin
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mpu: entity work.mips_mpu
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mpu: entity work.mips_mpu
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generic map (
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generic map (
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CLOCK_FREQ => CLOCK_FREQ,
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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)
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)
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port map (
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port map (
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interrupt => '0',
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interrupt => '0',
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Line 234... |
hex_display_register:
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hex_display_register:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
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if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
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reg_display <= io_wr_data(15 downto 0);
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reg_display(15 downto 0) <= io_wr_data(15 downto 0);
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--reg_display <= mpu_sram_address;
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end if;
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end if;
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end if;
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end if;
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end process hex_display_register;
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end process hex_display_register;
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sd_control_register:
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sd_control_register:
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Line 334... |
--##############################################################################
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--##############################################################################
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-- Use button 3 as reset
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-- Use button 3 as reset
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-- This FF chain only prevents metastability trouble, it does not help with
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-- This FF chain only prevents metastability trouble, it does not help with
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-- switching bounces.
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-- switching bounces.
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-- (NOTE: the anti-metastability logic is probably not needed when we include
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-- the debouncing logic)
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reset_synchronization:
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reset_synchronization:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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reset_sync(2) <= not buttons(3);
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reset_sync(3) <= not buttons(2);
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reset_sync(2) <= reset_sync(3);
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reset_sync(1) <= reset_sync(2);
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reset_sync(1) <= reset_sync(2);
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reset_sync(0) <= reset_sync(1);
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reset_sync(0) <= reset_sync(1);
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end if;
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end if;
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end process reset_synchronization;
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end process reset_synchronization;
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reset <= reset_sync(0);
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reset_debouncing:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset_sync(0)='1' and reset_sync(1)='0' then
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debouncing_counter <= (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
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else
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if debouncing_counter /= 0 then
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debouncing_counter <= debouncing_counter - 1;
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end if;
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end if;
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end if;
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end process reset_debouncing;
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--
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reset <= '1' when debouncing_counter /= 0 or pll_locked='0' else '0';
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-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
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-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
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process(clk_50MHz)
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process(clk)
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begin
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begin
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if clk_50MHz'event and clk_50MHz='1' then
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if clk'event and clk='1' then
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if reset = '1' then
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if reset = '1' then
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clk_1hz <= '0';
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clk_1hz <= '0';
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counter_1hz <= (others => '0');
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counter_1hz <= (others => '0');
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else
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else
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if conv_integer(counter_1hz) = 50000000 then
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if conv_integer(counter_1hz) = CLOCK_FREQ-1 then
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counter_1hz <= (others => '0');
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counter_1hz <= (others => '0');
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clk_1hz <= not clk_1hz;
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clk_1hz <= not clk_1hz;
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else
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else
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counter_1hz <= counter_1hz + 1;
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counter_1hz <= counter_1hz + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Master clock is external 50MHz oscillator
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-- Master clock is external 50MHz or 27MHz oscillator
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slow_clock:
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if CLOCK_FREQ = 27000000 generate
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clk <= clk_27MHz;
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pll_locked <= '1';
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end generate;
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fast_clock:
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if CLOCK_FREQ = 50000000 generate
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clk <= clk_50MHz;
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clk <= clk_50MHz;
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pll_locked <= '1';
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end generate;
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--pll_clock:
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--if CLOCK_FREQ /= 27000000 and CLOCK_FREQ/=50000000 generate
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---- Assume PLL black box is properly configured for whatever the clock rate is...
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--input_clock_pll: component pll
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-- port map(
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-- areset => '0',
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-- inclk0 => clk_50MHz,
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-- c0 => clk_pll,
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-- locked => pll_locked
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-- );
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--
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----clk <= clk_1hz when reg_display(31 downto 27)="10110" else clk_pll;
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--clk <= clk_pll;
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--end generate;
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--##############################################################################
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--##############################################################################
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-- LEDS, SWITCHES
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-- LEDS, SWITCHES
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--##############################################################################
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--##############################################################################
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| Line 349... |
Line 425... |
--##############################################################################
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--##############################################################################
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-- QUAD 7-SEGMENT DISPLAYS
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-- QUAD 7-SEGMENT DISPLAYS
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--##############################################################################
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--##############################################################################
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-- Show contents of debug register in hex display
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-- Show contents of debug register in hex display
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display_data <= reg_display;
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display_data <=
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reg_display(15 downto 0);-- when switches(0)='0' else
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--reg_display(31 downto 16);
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-- 7-segment encoders; the dev board displays are not multiplexed or encoded
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-- 7-segment encoders; the dev board displays are not multiplexed or encoded
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hex3 <= nibble_to_7seg(display_data(15 downto 12));
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hex3 <= nibble_to_7seg(display_data(15 downto 12));
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hex2 <= nibble_to_7seg(display_data(11 downto 8));
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hex2 <= nibble_to_7seg(display_data(11 downto 8));
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| Line 377... |
Line 455... |
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-- Embedded in the MPU entity
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-- Embedded in the MPU entity
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end minimal;
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end minimal;
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No newline at end of file
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No newline at end of file
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--------------------------------------------------------------------------------
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-- NOTE: Optional use of a PLL
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--
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-- In order to try the core with any clock other the 50 and 27MHz oscillators
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-- readily available onboard we need to use a PLL.
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-- Unfortunately, Quartus-II won't let you just instantiate a PLL like ISE does.
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-- Instead, you have to build a PLL module using the MegaWizard tool.
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-- A nasty consequence of this is that the PLL can't be reconfigured without
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-- rebuilding it with the MW tool, and a bunch of ugly binary files have to be
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-- committed to SVN if the project is to be complete.
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-- When I figure up what files need to be committed to SVN I will. Meanwhile you
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-- have to build the module yourself if you want to u se a PLL -- Sorry!
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-- At least it is very straightforward -- create an ALTPLL variation (from the
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-- IO module library) named 'pll' with a 45MHz clock at output c0, that's it.
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--
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-- Please note that the system will run at >50MHz when using 'balanced'
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-- synthesis. Only the 'area optimized' synthesis may give you trouble.
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--------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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